pi2eqx5804c Pericom Semiconductor Corporation, pi2eqx5804c Datasheet
pi2eqx5804c
Available stocks
Related parts for pi2eqx5804c
pi2eqx5804c Summary of contents
Page 1
... SCL 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ Description Pericom Semiconductor’s PI2EQX5804C is a low power, PCIe® compliant signal ReDriver™. The device provides programmable equalization, amplifi cation, and de-emphasis by using 8 select bits, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference ...
Page 2
... Selection pins for Channel Bx emphasis (See emphasis Confi guration Table 100K-Ohm internal pull up De-emphasis enable input for Channel A0, A1, A2 and A3 with internal 100K- I Ohm pull-up resistor. Set high selects output de-emphasis and set low selects output pre-emphasis. 2 PI2EQX5804C Equalization & Emphasis PS8926B 04/09/09 ...
Page 3
... Table) w/ 100K-Ohm internal pull SCL clock input SDA data input. Selection pins for Channel Ax equalization (see Equalizer Confi guration Table 100K-Ohm internal pull up 3 PI2EQX5804C Equalization & Emphasis 2 C control with internal 100k-ohm pull- opera- PS8926B 04/09/09 ...
Page 4
... Signal detect output pin for Channel A0. SIG_A=High represents a input signal > O threshold at the differential inputs. Signal detect output pin for Channel B0. SIG_B=High represents a input signal > O threshold at the differential inputs. PWR Supply Ground PWR 1.2V Supply Voltage 4 PI2EQX5804C Equalization & Emphasis 2 C control. When MODE is set high, PS8926B 04/09/09 ...
Page 5
... Output Confi guration The PI2EQX5804C provides fl exible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open- ing. Control of output confi guration is grouped for the A and B channels, so that each channel within the group has the same setting. Output confi ...
Page 6
... Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5804C to confi g- ure itself properly depending on the devices it is communicating with, whether 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card ...
Page 7
... PI2EQX5804C 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis Full IC power down, all channels dis- abled Channel disabled, output pulls to V Receiver detect reset Channel enabled, no input signal, output pulls to V ...
Page 8
... Loopback Operation Each lane of the PI2EQX5804C provides a loopback mode for test purposes which is controlled by a strapping 2 pin and I C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode is en- abled. When LB# is low the loopback mode is enabled. The fi gure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal system application is to initialize to one confi ...
Page 9
... VDD1 (1.2V), the sources (s) to the bus lines of the “Lower voltage” section, and the drains (d) to the bus lines of the “Higher voltage” section. The diode between the drain (d) and substrate is inside the MOS-FET present as n-p junction of drain and substrate. 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis 9 PI2EQX5804C 2 C- PS8926B 04/09/09 ...
Page 10
... 2SK3018 “Higher voltage” section Drain to Current - Con- Source Volt- tinuous Drain age (Vds) (Id) @ 25° C 30V 100mA 10 PI2EQX5804C Equalization & Emphasis VDD2= 3.3 V 10k 10k SDA SCL to I2C controller Input Capac- Gate Package / itance (Ciss) threshold Case @ Vds voltage ...
Page 11
... For a write cycle, the fi rst data byte fol- lowing the address byte is a dummy or fi ll byte that is not used by the PI2EQX5804C. This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most signifi ...
Page 12
... SIG_A1 SIG_B1 SIG_A2 RX50_A1 RX50_B1 RX50_A2 LB_A2B2# LB_A3B3# DE_A R/W R/W R/W LB# LB# DE_A 12 PI2EQX5804C Equalization & Emphasis SIG_B2 SIG_A3 SIG_B3 RX50_B2 RX50_A3 RX50_B3 DE_B rsvd rsvd R/W R ...
Page 13
... INDIS_A1 INDIS_B1 INDIS_A2 R/W R/W R ODIS_A1 ODIS_B1 ODIS_A2 R/W R/W R RES_A1# RES_B1# RES_A2# R/W R/W R/W RESET# RESET# RESET# 13 PI2EQX5804C Equalization & Emphasis INDIS_B2 INDIS_A3 INDIS_B3 R/W R/W R ODIS_B2 ODIS_A3 ODIS_B3 R/W R/W R RES_B2# RES_A3# RES_B3# R/W R/W R/W RESET# RESET# ...
Page 14
... PD_A1# PD_B1# PD_A2# R/W R/W R/W PD# PD# PD RXD_A1 RXD_B1 RXD_A2 R/W R/W R/W RXD_A RXD_B RXD_A SEL2_A D0_A D1_A R/W R/W R/W SEL2_A D0_A D1_A 14 PI2EQX5804C Equalization & Emphasis PD_B2# PD_A3# PD_B3# R/W R/W R/W PD# PD# PD RXD_B2 RXD_A3 RXD_B3 R/W R/W R/W RXD_B RXD_A RXD_B D2_A S0_A S1_A R/W R/W R/W D2_A ...
Page 15
... HIGH transition on the SDA line while SCL is HIGH defi nes a STOP condition, as shown in the fi gure below. 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with SEL2_B D0_B D1_B R/W R/W R/W SEL2_B D0_B D1_B 2 C interface. These bytes are R/W, are initialized PI2EQX5804C Equalization & Emphasis D2_B S0_B S1_B R/W R/W R/W D2_B S0_B S1_B PS8926B 04/09/09 ...
Page 16
... I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. 16 PI2EQX5804C 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis ACK DATA OUT N ...
Page 17
... A Conditions = 0 TO 70°C) A Conditions 17 PI2EQX5804C 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis Note: Stresses greater than those listed under MAXI- MUM RATINGS may cause permanent damage to the device. This is a stress rating only and function al operation of the device at these or any other condi- tions above those indicated in the operational sections of this specifi ...
Page 18
... A Conditions Single ended |VTX-D+ - VTX-D-| VTX-DIFFP VTX-D+ - VTX- VTX-D+ + VTX- 20% to 80% ( 70°C) A Conditions Min. VDD/2 +0 4mA VDD-0 4mA OL 18 PI2EQX5804C Equalization & Emphasis Min. Typ. Max. 0.3 0.2 1.5 Min. Typ. Max 100 120 200 800 0.4 1.6 VDD- 0.3 ...
Page 19
... A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the V fi ned region of the falling edge of SCL. 09-0044 (V = 1.2 ± 0.05v 70° Conditions I = 3mA OL Conditions levels. 19 PI2EQX5804C 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis Min. Typ. Max. 1.1 VDD+0.3 -0.3 0.7 0.4 0.2 2 (1) C-bus devices Min ...
Page 20
... START SDA t SU;DAT LOW SCL t HD;STA t HD;DAT S 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with HD;STA t SU;STA HIGH Timing Channel Latency, 5.0 Gbps 20 PI2EQX5804C Equalization & Emphasis STOP START BUF t SU;STO P S PS8926B 04/09/09 ...
Page 21
... Output Level Settings (1V left, and 0.5V right at 5.0 Gbps) 0.0 dB (Dx = 000) –6.5 dB (Dx = 101) Output De-emphasis Characteristics 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis –3.5 dB (Dx = 010) –8.5 dB (Dx = 111) 21 PI2EQX5804C PS8926B 04/09/09 ...
Page 22
... Eye Diagrams 5.0Gbps (input left, output right) Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right) Signal Source Connector AC Test Circuit Referenced in the Electrical Characteristic Table 09-0044 5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with FR4 A B SmA SmA Connector ≤ PI2EQX5804C Equalization & Emphasis C D.U.T. In Out PS8926B 04/09/09 ...
Page 23
... Low Profile Ball Grid Array (LBGA) NJ100 Package Code Package Description NJ Pb-free & Green 100-Contact LBGA 23 ® (www.pcisig.com) PI2EQX5804C Equalization & Emphasis 2055 PS8926B 04/09/09 ...