pi2eqx5864d Pericom Semiconductor Corporation, pi2eqx5864d Datasheet - Page 11

• Manufacturer Part Number: pi2eqx5864d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization, Emphasis, & I2c Control
• Manufacturer: Pericom Semiconductor Corporation

BYTE 5 - Channel Reset (RESET)
RESET# =0=reset, RESET# =1=normal operation. Latch from RESET# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates
a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RESET# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXDETEN)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
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Bit
Type
Power-on
State
Bit
Type
Power-on
State
Bit
Type
Power-on
State
Name
Name
Name
7
RXDE-
TEN_A0
R/W
Latch from RXD_A & RXD_B inputs at startup
7
R/W
Latch from RESET# inputs at startup
RESET_
A0#
7
R/W
1
PD_A0#
6
R/W
6
R/W
RXDE-
TEN_B0
RESET_
B0#
6
R/W
1
PD_B0#
5
R/W
5
R/W
RXDE-
TEN_A1
RESET_
A1#
5
R/W
1
PD_A1#
10-0172
4
R/W
4
R/W
RESET_
B1#
RXDE-
TEN_B1
4
R/W
1
PD_B1#
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
11
3
R/W
3
RXDE-
TEN_A2
R/W
RESET_
A2#
3
R/W
1
PD_A2#
2
R/W
2
R/W
RESET_
B2#
RXDE-
TEN_B2
2
R/W
1
PD_B2#
www.pericom.com
1
R/W
1
R/W
RESET_
A3#
RXDE-
TEN_A3
1
R/W
1
PD_A3#
PI2EQX5864D
PS 0.1
0
R/W
RESET_
B3#
0
R/W
0
R/W
1
RXDE-
TEN_B3
PD_B3#
06/04/10