ncn6024 ON Semiconductor, ncn6024 Datasheet - Page 10

• Manufacturer Part Number: ncn6024
• Description: Compact And Low Cost Smart Card Interface Ic
• Manufacturer: ON Semiconductor

resistor divider R1 / R2 (see block diagram Figure 1) and the
PORADJ internal 5 mA pull−down current source Ipd :
threshold (VDD falling) is typically 2.35 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the VDD supply dropout detection
level which enables a deactivation sequence if the VDD
voltage is too low.
minimum supply voltage insuring a correct operating is
higher than 2.55 V, increasing UVLO
consequently necessary. Considering for instance a resistor
bridge with R1 = 56 kW, R2 = 42 kW and V
typical the VDD dropout detection level can be increased up to:
than 2 V.
CLOCK DIVIDER:
depending upon the specific application, prior to be applied
to the smart card driver. These division ratios are
programmed using pins CLKDIV1 and CLKDIV2 (see
Table 1). The input clock is provided externally to pin
CLKIN.
maximum frequency signal (considering a division ratio w
2). Of course, the ratio must be defined by the user to cope
with Smart Card considered in a given application
range specification, the divider is synchronized by the last
flip flop, thus yielding a constant 50% duty cycle, whatever
be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the
output signal Duty Cycle cannot be guaranteed 50% if the
division ratio is 1 and if the input Duty Cycle signal is not
within the 46 − 56% range at the CLKIN input.
external controller, the clock will be applied to the card
under the control of the microcontroller or similar device
after the activation sequence has been completed.
DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS
AUX2 adapt the voltage difference that might exist between
the micro-controller and the smart card. These three
Table 1. Clock Frequency Programming
If PORADJ is connected to Ground the VDD UVLO
For example, there’re microcontrollers for which the
The minimum dropout detection voltage should be higher
The maximum detection level may be up to VDD.
The input clock can be divided by 1/1, 1/2, 1/4, or 1/8,
The clock input stage (CLKIN) can handle a 27 MHz
In order to avoid any duty cycle out of the 45% / 55%
When the signal applied to CLKIN is coming from the
The three bidirectional level shifters I/O, AUX1 and
UVLO + 59k ) 42k
CLKDIV1
0
0
1
1
42k
UVLO + R1 ) R2
V
CLKDIV2
POR−
0
1
0
1
R2
) 56k
V
VDD
POR
5 mA + 3.03 V
) R1 Ipd
(VDD falling) is
CKLKIN / 4
F
POR-
CLKIN / 2
CLKIN/8
CRD_CLK
CLKIN
= 1.18 V
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channels are identical. The first side of the bidirectional
level shifter dropping Low (falling edge) becomes the driver
side until the level shifter enters again in the idle state pulling
High CRD_IO and I/Ouc.
integrated on each terminal of the bidirectional channel. In
addition with these pull-up resistors, an active pull-up
circuit provides a fast charge of the stray capacitance.
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
STANDBY MODE
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
•
•
•
•
•
POWER-UP
presence of a card using the signals INT and CMDVCC as
shown in Table 2:
active) the controller can start a card session by pulling
CMDVCC Low. Card activation is run (t0, Figure 5). This
Power−Up Sequence makes sure all the card related signals
are LOW during the CRD_VCC positive going slope. These
lines are validated when CRD_VCC is stable and above the
minimum voltage specified. When the CRD_VCC voltage
reaches the programmed value (3.0 V or 5.0 V), the circuit
activates the card signals according to the following
sequence:
•
•
•
•
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. In these initial conditions CRD_CLK starts when
RSTIN is pulled Low. This allows a precise count of clock
pulses before toggling CRD_RST High for ATR
(Answer To Reset) request.
Table 2. Card Presence State
Passive 11 kW pull-up resistors have been internally
The current to and from the card I/O lines is limited
After a Power-on reset, the circuit enters the standby
In the standby mode the microcontroller can check the
If a card is detected present (CRD_PRES or CRD_PRES
The clock can also be applied to the card using a RSTIN
All card contacts are inactive
Pins I/Ouc, AUX1uc and AUX2uc are in the
high-impedance state (11 kW pull−up resistor to VDD)
Card pins are inactive and pulled Low
Supply Voltage monitoring is active
The internal DC/DC converter oscillator is running.
CRD_VCC is powered-up at its nominal value (t1)
I/O, AUX1 and AUX2 lines are activated (t2)
Then Clock channel is activated and the clock signal is
applied to the card (t3)
Finally the Reset level shifter is enabled (t4)
HIGH
LOW
INT
CMDVCC
HIGH
HIGH
Card not present
Card present
State