pxb4360f Infineon Technologies Corporation, pxb4360f Datasheet - Page 45

• Manufacturer Part Number: pxb4360f
• Description: Content Addressable Memory Element Came
• Manufacturer: Infineon Technologies Corporation

All communication with ALP is done using the data interface. The data interface consists of the
following signals, as shown in
1)
CAME will be accessed only if CE is low at the rising edge of CLK. If WE is low at the time, a
write cycle will be executed; if WE is high, a read cycle will be executed. The OE signal controls
the CAME output buffers for read accesses only. The EN16 signal determines data bus width,
which is 16-bit for EN16 at low level, and 32-bit otherwise. This signal is intended for static
adjustment of bus width.
Parity generation in 16-bit Mode extends over DAT(16..0) and ADR(3..0). In 32-bit Mode, it
extends over DAT(32..0) and ADR(3..0). In 32-bit interface mode, ADR(3) is not needed and
must be connected to ground; thus, parity generated over DAT(32..0) and ADR(2..0) is accepted
correctly. In both cases, DAT(0) is used as a parity line and completes the corresponding DAT
and ADR lines to odd parity. In 16-bit Mode, only the lower part of the data bus is used. The
upper bus half (index 17..32) is ignored during write accesses to CAME and is 0 during read
accesses.
Data Sheet
DAT(0)
DAT(31..1)
DAT(32)
ADR(2..0)
ADR(3)
WE
OE
CE
CLK
EN16
DAT(15:1) are needed with ALP V1.1. DAT(32:17) are reserved for future use.
1)
Odd parity. Selected to create parity over ADR and DAT bidirectional
Data Bus
Data Bus
Address Bus
Address Bus
Write Enable
Output Enable
Chip Enable
Clock
Selection of bus width
:
6-45
bidirectional
bidirectional
input
input
input
input
input
input
input
07.2000