adg836 Analog Devices, Inc., adg836 Datasheet - Page 7

• Manufacturer Part Number: adg836
• Description: 0.5 ? Cmos 1.65 V To 3.6 V Dual Spdt/2 1 Mux
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATIONS
Table 6. Terminology
V
I
GND
S
D
IN
V
R
R
∆R
I
I
I
V
V
I
C
C
C
C
t
t
t
Charge Injection
Off Isolation
Crosstalk
−3 dB Bandwidth
On Response
Insertion Loss
THD + N
DD
S
D
D
INL
ON
OFF
BBM
DD
D
ON
FLAT (ON)
INL
INH
S
D
D
IN
, I
(OFF)
(OFF)
, C
ON
(OFF)
(V
(OFF)
S
(I
(ON)
INH
S
S
)
(ON)
)
GND
S1A
S2A
IN1
IN2
Figure 2. 10-Lead MSOP (RM-10)
Ground (0 V) reference.
Logic control input.
Analog voltage on terminals D, S.
Source leakage current with the switch off.
Channel leakage current with the switch on.
Input current of the digital input.
Off switch source capacitance. Measured with reference to ground.
Off switch drain capacitance. Measured with reference to ground.
On switch capacitance. Measured with reference to ground.
Most positive power supply potential.
Positive supply current.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Ohmic resistance between D and S.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
On resistance match between any two channels.
Drain leakage current with the switch off.
Maximum input voltage for Logic 0.
Minimum input voltage for Logic 1.
Digital input capacitance.
Delay time between the 50% and the 90% points of the digital input and switch on condition.
Delay time between the 50% and the 90% points of the digital input and switch off condition.
On or off time measured between the 80% points of both switches when switching from one to another.
A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.
A measure of unwanted signal coupling through an off switch.
A measure of unwanted signal, which is coupled through from one channel to another, as a result of parasitic
capacitance.
The frequency at which the output is attenuated by 3 dB.
The frequency response of the on switch.
The loss due to the on resistance of the switch.
The ratio of the harmonics amplitude plus noise of a signal to the fundamental.
1
2
3
4
5
(Not to Scale)
ADG836
TOP VIEW
10
9
8
7
6
D1
S1B
V
S2B
D2
DD
Rev. A | Page 7 of 16
NC = NO CONNECT
Figure 3. 12-Lead LFCSP (CP-12)
GND
S1A
S2A
1
2
3
(Not to Scale)
ADG836
TOP VIEW
PIN 1
INDICATOR
9 S1B
8 V
7 S2B
DD
ADG836