adv3002 Analog Devices, Inc., adv3002 Datasheet - Page 12

• Manufacturer Part Number: adv3002
• Description: 4 1 Hdmi/dvi Switch With Equalization, Ddc/cec Buffers And Edid Replication
• Manufacturer: Analog Devices, Inc.

ADV3002
THEORY OF OPERATION
The primary function of the ADV3002 is to switch up to four
HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI
link consists of four differential, high speed channels and four
auxiliary single-ended, low speed signals. The high speed channels
include a data-word clock and three transition minimized differential
signaling (TMDS) data channels running at 10× the data-word
clock frequency for data rates up to 2.25 Gbps. The four low speed
control signals are the display data channel (DDC) bus (SDA and
SCL), the consumer electronics control (CEC) line, and the hot
plug detect (HPD) signal.
The ADV3002 also includes an integrated EDID SRAM, eliminating
the need for an external EDID EEPROM for each HDMI connector.
A typical HDMI multiplexer is shown in Figure 19. The simplified
implementation using the ADV3002 is shown in Figure 20.
TMDS INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown in
Figure 21. The state of the input terminations can be configured
automatically or programmed manually by setting the appropriate
bits in the TMDS input termination control register, as shown in
Table 10.
Figure 20. Simplified Implementation Using the ADV3002
DDC
5V
DDC
5V
DDC
5V
DDC
5V
Figure 19. Typical HDMI Multiplexer Implementation
DDC
5V
DDC
5V
DDC
5V
DDC
5V
EDID A
EDID B
EDID C
EDID D
2
2
2
2
2
2
2
2
ADV3002
HDMI
MUX
4:1
AMUXVCC
MICROCONTROLLER
EDID EEPROM
OR SYSTEM
EXTERNAL
DDC
DDC
2
2
2
EDID DDC
HDMI
HDMI
Rx
Rx
Rev. 0 | Page 12 of 28
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 18 dB. The
equalizer (EQ) level defaults to 18 dB after reset. No specific cable
length is suggested for a particular equalization setting because
cable performance varies widely between manufacturers; however,
in general, the equalization of the ADV3002 can be set to 18 dB
without degrading the signal integrity, even for short input cables.
TMDS OUTPUT CHANNELS
Each high speed output differential pair is terminated to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown
in Figure 22. This termination is user-selectable; it can be turned
on or off by programming the TX_OTO bit of the TMDS output
control register, as shown in Table 10.
The output termination resistors of the ADV3002 back terminate
the output TMDS transmission lines. These back terminations, as
recommended in the HDMI 1.3a specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the ADV3002 TMDS outputs
on multiple layers of the printed circuit board (PCB) without
severely degrading the quality of the output signal.
The output has a disable feature that places the outputs in tristate
mode. Bigger wire-OR’ e d arrays can be constructed using the
ADV3002 in this mode.
The ADV3002 requires output termination resistors when the high
speed outputs are enabled. Termination can be internal and/or
external. The internal terminations of the ADV3002 are enabled
by default after reset. External terminations can be provided either
by on-board resistors or by the input termination resistors of an
OUT+
NOTES
1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS.
2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS.
IN+
IN–
Figure 22. High Speed Output Simplified Schematic
NOTES
1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS.
2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS.
Figure 21. High Speed Input Simplified Schematic
AVEE
DISABLE
AVCC
50Ω
AVCC
AVEE
I
OUT
50Ω
50Ω
50Ω
OUT–
CABLE
EQ
PROT.
ESD