psf2115 ETC-unknow, psf2115 Datasheet - Page 301
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psf2115
Manufacturer Part Number
psf2115
Description
Isdn Adapter Circuit Ipac
Manufacturer
ETC-unknow
Datasheet
1.PSF2115.pdf
(317 pages)
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Semiconductor Group
7
The following chapters contain a quick reference guide.
7.1
MON-8 Configuration Register
In the configuration register the user programs the IPAC for different operational modes,
and selects required S-bus features.
The following paragraphs describe the application relevance of all individual
configuration register bits.
Address: 1h MFD
Value after Reset: 00
MFD
FSMM
LP
Appendix
MON-8 Registers
Multi-Frame-Disable. Selects whether multiframe generation (LT-S) or
synchronization (TE, LT-T) is prohibited (MFD=1) or allowed (MFD=0).
Enable multiframing if S/Q channel data transfer is desired. If MFD=1 no
S/Q MONITOR messages are released.
When reading this register the bit indicates whether multiframe
synchronization has been established (MFD=1) or not (MFD=0).
Finite State Machine Mode. By programming this bit the user has the
possibility to exchange the state machines of LT-S and NT, i.e. an IPAC pin
strapped for LT-S operates with a NT state machine. All other operation
mode specific characteristics are retained.
This function is used in intelligent NT configurations where the IPAC needs
to be pin-strapped to LT-S mode but the state machine of an NT is desirable.
Loop Transparency. In case analog loop-backs are closed with C/I = ARL or
bit SC in the loop-back register, the user may determine with this bit,
whether the data is forwarded to the S/T-interface outputs (transparent) or
not. The default setting depends on the operational mode.
TE/LT-T modes:0 =non transparent
1 =transparent ext. loop
LT-S mode:0 =transparent
1 = non transparent
In LT-S by default transparency is selected (LP=0), for LT-T and TE non-
transparency is standard (LP=0).
H
0
FSMM
LP
301
SQM RCVE C/W/P
0
PSB 2115
PSF 2115
Appendix
RD/WR
11.97
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