zxcw8100 Diodes, Inc., zxcw8100 Datasheet - Page 9

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zxcw8100

Manufacturer Part Number
zxcw8100
Description
32 Bit Stereo Direct Drive Digital Audio Amplifier
Manufacturer
Diodes, Inc.
Datasheet
BLOCK DIAGRAM
FUNCTIONAL DEVICE DESCRIPTION
The ZXCW8100 device is an integrated stereo digital
amplifier. It takes in digital audio data, in any of the
common digital audio formats, processes it and
delivers a PWM direct drive left and right channel
output. The direct drive PWM output can be used to
drive full bridge tied load output stages configured to
deliver typical power in the range 10W to 50W and
above.
SPI Interface
The device is controlled by a 3 wire SPI interface. The 8
bit control and 64 bit data words directed through the
SPI interface are used to control all the functions of the
ZXCW8100 device:
The SPI interface is bi-directional such that the
appropriate programmed configuration and data can
be read back if required.
ISSUE 3 - NOVEMBER 2003
Volume/Mute
Bass/Treble
De-emphasis
NOVALOAD™
Audio data format
ATAPI CD-ROM standard
PWM drive outputs
Auto power low
Speed mode
9
Format converter
The format converter ensures the device is compatible
with all the normal digital input standards. The
standards supported are:
The audio data for left and right channels is transmitted
in the high and low periods of the word clock
depending on the format chosen. The first received
audio data is held until the corresponding channel data
is received. The left and right channels data are then
processed in parallel. The word clock represents the
sampling rate of the audio data input, also referred to
as Fs.
Volume
Digital volume control is achieved through the SPI port.
Volume can be set anywhere in the range of -94.5dB to
+25dB in 0.5dB steps. A code is included in the volume
register to enable a soft mute function to be achieved,
this set to -95dB.
A digital silence function is also available, this is
selected by activating the auto low power mode. In this
case, if no serial digital data is detected for a period of
4096 word clocks then the output stage is switched off.
In this mode minimum EMC signature is experienced.
24 and 32 bit I
Left justify 24 or 32 bit
Right justify 16 bit
Right justify 24 bit
2
ZXCW8100S28
S
S E M I C O N D U C T O R S

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