clc425 National Semiconductor Corporation, clc425 Datasheet - Page 8

• Manufacturer Part Number: clc425
• Description: Ultra Low Noise Wideband Op Amp
• Manufacturer: National Semiconductor Corporation

Low Noise Integrator
The CLC425 implements a deBoo integrator shown in
Figure 15. Integration linearity is maintained through
positive feedback. The CLC425's low input offset
voltage and matched inputs allowing bias current
cancellation provide for very precise integration. Stabil-
ity is maintained through the constraint on the circuit
elements.
High-Gain Sallen-Key Active Filters
The CLC425 is well suited for high-gain Sallen-Key type
of active filters. Figure 16 shows the 2
low pass filter topology. Using component predistortion
methods as discussed in OA-21 enables the proper
selection of components for these high-frequency filters.
Low Noise Magnetic Media Equalizer
The CLC425 implements a high-performance low-noise
equalizer for such applications as magnetic tape
channels as shown in Figure 17. The circuit combines an
integrator with a bandpass filter to produce the low-
noise equalization. The circuit's simulated frequency
response is illustrated in Figure 18.
http://www.national.com
50
0.1 F
Figure 16: Sallen-Key Active Filter Topology
V
P
Figure 14: Very Low Noise Figure Amplifier
i
in
Mini-Circuits
T16-6T
1:4
R
R
1
Figure 15: Low Noise Integrator
a
V
C
o
R
2
1pF
806
V
C
10
in
2
R
sR C
20
K
CLC425
Gain = P
a
o
180
R
R
C
A
g
g
;
1
v
=+10
CLC425
CLC425
40k
50k
P
R
R
R
o
i
b
f
f
K
R R
= 35.6dB
R
a
200
o
||
b
20
1
nd
order Sallen-Key
R
R
50
CLC404
R
R
V
g
f
o
600
g
,
f
A
R
v
=-3
50
R
50
a
P
50
o
8
Low-Noise Phase-Locked Loop Filter
The CLC425 is extremely useful as a Phase-Locked
Loop filter in such applications as frequency synthesiz-
ers and data synchronizers. The circuit of Figure 19
implements one possible PLL filter with the CLC425.
Decreasing the Input Noise Voltage
The input noise voltage of the CLC425 can be reduced
from its already low 1.05nV/ Hz by slightly increasing the
supply current. Using a 50k resistor to ground on pin 8,
as shown in the circuit of Figure 14, will increase the
quiescent current to 17mA and reduce the input noise
voltage to < 0.95nV/ Hz.
Printed Circuit Board Layout
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes
to ground will cause frequency response peaking and
possible circuit oscillation, see OA-15 for more informa-
tion. National suggests the CLC730013-DIP,
CLC730027-SOIC, or CLC730068-SOT evaluation
board as a guide for high-frequency layout and as an aid
in device testing and characterization.
V
V
in
o
K
Figure 17: Low Noise Magnetic Media Equalizer
o
V
in
Figure 18: Equalizer Frequency Response
sC R
V
R
Figure 19: Phased-Locked Loop Filter
in
1
sC R
2 =
L
=
1
1
200
0.1 H
R
1
C
R
R
=
1 =
R
g
1
681
1 =
R
2200pF
1
b
45.3
R
R
CLC425
f
R
C
f
R
f
=
g =
R
470pF
g
50
C
s LCR R
f
2
2
R
CLC425
K
g
f =
V
o
out
1k
sL R
sLR
1
R
g
2
R
g
f
R
g
V
o
R R
2
g