clc411 National Semiconductor Corporation, clc411 Datasheet - Page 5

• Manufacturer Part Number: clc411
• Description: High-speed Video Op Amp With Disable
• Manufacturer: National Semiconductor Corporation

non-zero R
operational amplifiers such as the CLC411. Application
note OA-13, “Current-Feedback Loop-Gain Analysis
and Performance Enhancements,” explains the
ramifications of R
frequency response with respect to gain. The equations
found in the application note should be considered as a
starting point for the selection of R
not factor in the effects of parasitic capacitance found
on the inverting input, the output nor across the feedback
resistor. Equations in OA-13 require values for R
(301 ), Av (+2) and R
Combining these values yields a Z
transimpedance) of 400 . Figure 4 entitled
"Recommended R
the feedback resistor that provides a maximally flat
frequency response for the CLC411 over its gain range.
Gate
Gate
TTL
ECL
Disable
Figure 5B: Differential ECL Interface
-5.2V
50
f
330
Figure 5A: Disable Interface
must be used with current-feedback
330
Figure 5C: ECL Interface
-5.2V
Figure 5D: TTL Interface
f
+15V
and how to use it to tailor the desired
f
vs. Gain" will enable the selection of
Q1
3.57k
Q3
Q1
Q1
Q1
i
(inverting input resistance, 50 ).
332
-15V
Gate
ECL
Q2
Q2
Q2
0.1 F
Q2
Q4
0.1 F
-5.2V
t
50
330
50
* (optimum feedback
CLC411 pin 8, DISABLE
10k
f
. The equations do
V
th
Q1,Q2 MPSH10
Q3,Q4 MPSH81
-15V
0.1 F
931
0.1 F
1N914
f
5
The linear portion of the two curves (i.e. A
from the limitation on R
Enable/Disable Operation
The disable feature allows the outputs of several CLC411
devices to be connected onto a common analog bus
forming a high-speed analog multiplexer. When disabled,
the output and inverting inputs of the CLC411 become
high impedances. The disable pin has an internal pull-
up resistor which is pulled-up to an internal voltage, not
to the external supply. The CLC411 is enabled when pin
8 is left open or pulled-up to
grounded or pulled below
necessary to drive the disable pin. For example, CMOS
logic with V
temperature. TTL voltage levels are inadequate for
controlling the disable feature.
For faster enable/disable operation than 15V CMOS
logic devices will allow, the circuit of Figure 5 is
recommended. A fast four-transistor comparator, Figure
5A, interfaces between the CLC411 DISABLE pin and
several standard logic families. This circuit has a
differential input between the bases of Q1 and Q2. As
such it may be driven directly from differential ECL
logic, as in shown in Figure 5B. Single-ended logic
families may also be used by establishing an appropriate
threshold voltage on the V
Figures 5C and 5D illustrate a single-ended ECL and
TTL interface respectively. The Disable input, the base
of Q1, is driven above and below the threshold, V
Fastest switching speeds result when the differential
voltage between the bases of Q1 and Q2 is kept to less
A
B
C
DD
Figure 6: General Multiplexing Circuit
+
0
1
2
3
4
5
6
7
7V will guarantee proper operation over
g
(i.e. R
+
3V. CMOS logic devices are
th
input, the base of Q2.
DIS (pin 8)
+
Buffers
g
DIS (pin 8)
7V and disabled when
50 ).
+
+
-
-
A
B
CLC411
http://www.national.com
CLC411
V
>4) results
th
.