ncy9100 ON Semiconductor, ncy9100 Datasheet - Page 4

• Manufacturer Part Number: ncy9100
• Description: Compandor
• Manufacturer: ON Semiconductor

Circuit Description
the block diagram, are a full−wave rectifier, a variable gain
cell, an operational amplifier and a bias system. The
arrangement of these blocks in the IC result in a circuit
which can perform well with few external components, yet
can be adapted to many diverse applications.
flows from the rectifier input, to an internal summing node
which is biased at V
an external filter capacitor tied to the C
the average value of the input current controls the gain of the
variable gain cell. The gain will thus be proportional to the
average value of the input signal for capacitively−coupled
voltage inputs as shown in the following equation. Note that
for capacitively−coupled inputs there is no offset voltage
capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally)
which is less than 0.1 mA.
input signal levels is determined by the rectifier filter
capacitor. A small capacitor will yield rapid response but
will not fully filter low frequency signals. Any ripple on the
gain control signal will modulate the signal passing through
the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so
there is a trade−off to be made between fast attack and decay
times and distortion. For step changes in amplitude, the
change in gain with time is shown by this equation.
with the ratio I
current which flows from the DG input to an internal
summing node biased at V
applies for capacitively−coupled inputs. The output current,
I
compensates for temperature and cancels out odd harmonic
distortion. The only distortion which remains is even
harmonics, and they exist only because of internal offset
voltages. The THD trim terminal provides a means for
nulling the internal offsets for low distortion operation.
compensated) has the non−inverting input tied to V
the inverting input connected to the DG cell output as well
OUT
The NCY9100 compandor building blocks, as shown in
The full−wave rectifier rectifies the input current which
The speed with which gain changes to follow changes in
The variable gain cell is a current−in, current−out device
A compensation scheme built into the DG cell
The
, is fed to the summing node of the op amp.
G(t) + (G
operational
t + 10kW
OUT
I
IN
G T
/I
initial
REF
+
IN
G T
. The rectified current is averaged on
amplifier
controlled by the rectifier. I
V
|V
* G
IN
IN
C
| V
* V
* V
R
or
RECT
REF
final
2
IN
R
R
REF
REF
| avg
) e
1
1
. The following equation
*t
(which
t
| avg
+
) G
V
R
RECT
IN
2
final
is
terminal, and
internally
REF
IN
http://onsemi.com
is the
, and
4
as brought out externally. A resistor, R
the summing node and allows compressor or expander gain
to be determined only by internal components.
This allows a +13 dBm (3.5 V
which, with a series resistor and proper transformer, can
result in +13 dBm with a 600 W output impedance.
summing nodes, a regulated supply voltage for the rectifier
and DG cell, and a bias current for the DG cell. The low
tempco of this type of reference provides very stable biasing
over a wide temperature range.
shows the basic input−output transfer curve for basic
compressor or expander circuits.
V
V
The output stage is capable of ± 20 mA output current.
A bandgap reference provides the reference voltage for all
The typical performance characteristics illustration
2.2mF
2.2mF
1
3, 14
2, 15
2
Figure 2. Basic Input−Output Transfer Curve
20kW
10kW
13
+20
+10
−10
−20
−30
−40
−50
−60
−70
−80
4
Figure 3. Typical Test Circuit
V
−40
0
CC
EXPANDOR INPUT LEVEL (dBm)
COMPRESSOR OUTPUT LEVEL
0.1mF
= 15V
DG
1, 16
2.2mF
−30 −20 −10
RMS
OR
5, 12
8.2kW
30kW
) output into a 300 W load
20kW
−
+
10mF
V
3
0
REF
, is brought out from
8, 9
+10
200pF
6, 11
7, 10
V
O