sc1109acstrt Semtech Corporation, sc1109acstrt Datasheet - Page 6

• Manufacturer Part Number: sc1109acstrt
• Description: Sc1109 Synchronous Pwm Controller With Dual Low-dropout Regulator Controllers
• Manufacturer: Semtech Corporation

THEORY OF OPERATION
The SC1109 has integrated a synchronous buck control-
ler and two Low drop out regulator controllers into a 16
Pin SOIC package. The switching regulator provides a 1.2V
(VTT) bus termination voltage for use in AGTL (Assisted
Gunning Transceiver Logic), while the dual LDO regulators
provide 1.5V, and 1.8V to power up the Chip set and the
Clock circuitry used in Pentium
SUPPLIES
Two supplies, VSTBY, and VCC are used to power the
SC1109 . VSTBY supply provides the bias for the Internal
Reference, Oscillator, and the LDO FET controllers. This
supply should always be brought up first and turned off
last in accordance with PC power configuration require-
ments. The VCC supply provides the bias for the Power
Good circuitry, and the high side FET Rdson sensing/
over current circuitry, VCC also is used to drive the low
side MOSFET gate. An external 12V supply or a classical
boot strapping technique can provide the gate drive for
the upper Mosfet.
PWM CONTROLLER
SC1109 is a voltage mode buck controller that utilizes an
internally compensated high bandwidth error amplifier to
sense the VTT output voltage. External compensation com-
ponents are not needed and a stable closed loop re-
sponse is insured due to the internal compensation.
START UP SEQUENCE
Initially during the power up, the SC1109 is in under volt-
age lockout condition. The latch (SET dominant) in the
hiccup section is set , and the SS/EN pin is pulled low by
the 2µA soft start current source.
Mean while, the high side and low side gate drivers DH,
and DL are kept low. Once the VCC exceeds the UVLO
threshold of 4.2V, the latch is reset and the external soft
start capacitor starts to be charged by a 10µA current
source.
The gate drives are still kept off until the soft start ca-
pacitors voltage rises above 600mV, when the low side
gate is turned on, and the high side gate is kept off.
POWER MANAGEMENT
Application Information
2004 Semtech Corp.
®
III Motherboards.
6
The gate drive status stays the same until the capacitors
voltage reaches 1V, when the error amplifier output starts
to cross the oscillator triangular ramp of 1V to 2V.
As the SS/EN pin continues to rise, the error amplifier
output also rises at the same rate and the duty cycle
increases.
Once the VTT output has reached regulation and is within
1.2V ± 12% , an open collector power good flag is acti-
vated, and the error amplifier output will no longer be
clamped to the SS/EN voltage and will stay between 1V
to 2V and maintain regulation of ± 1%. The SS/EN volt-
age continues to rise up to 2.5V and will stay at that
voltage level during normal operation.
If an over current condition occurs, the SS/EN pin will
discharge by a 2µA current source, from 2.5V to 800mV.
During this time both DH, and DL will be turned off. Once
the SS/EN reaches 800mV, the low side gate will be
turned on, and the SS/EN pin will again start to be charged
by the 10µA current source, and the same soft start se-
quence mentioned above will be repeated.
OVER CURRENT
SC1109A/B monitor the Upper MOSFETs Rdson voltage
drop due to an over current condition. This method of cur-
rent sensing minimizes any unnecessary losses due to ex-
ternal sense resistance.
PowerGood
PhaseNode
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SC1109
Soft start
Vcc