74lcxz16240 Fairchild Semiconductor, 74lcxz16240 Datasheet
74lcxz16240
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74lcxz16240 Summary of contents
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... MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74LCXZ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
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Truth Tables Inputs OE I – Inputs OE I – HIGH Voltage Level L LOW Voltage Level X Immaterial Z High ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ t Output to Output Skew (Note 5) OSHL t OSLH Note 5: ...
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AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C 6V for for V CC Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times ...
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Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 Preliminary ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 7 Preliminary www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...