DS1982-F3 Maxim Integrated Products, DS1982-F3 Datasheet
DS1982-F3
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DS1982-F3 Summary of contents
Page 1
... Reduces control, address, data, power, and programming signals to a single data pin 8-bit family code specifies DS1982 communications requirements to reader Reads over a wide voltage range of 2.8V to 6.0V from -40°C to +85°C; programs at 11.5V to 12.0V from -40°C to +50°C ...
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... ORDERING INFORMATION DS1982-F3 F3 MicroCan DS1982-F5 F5 MicroCan iButton DESCRIPTION The DS1982 1-kbit Add-Only iButton is a rugged read/write data carrier that identifies and stores relevant information about the product or person to which it is attached. This information can be accessed with minimal hardware, for example, a single port pin of a microcontroller. The DS1982 consists of a factory- lasered registration number that includes an unique 48-bit serial number, an 8– ...
Page 3
... Figure 6. All data is read and written least significant bit first. 64-BIT LASERED ROM Each DS1982 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3). ...
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... DS1982 BLOCK DIAGRAM Figure DS1982 ...
Page 5
... SEARCH ROM SKIP ROM WRITE MEMORY WRITE STATUS BYTE READ MEMORY READ STATUS BYTE READ DATA/GENERATE 8-BIT CRC 48- Bit Serial Number LSB MSB DS1982 OTHER DEVICES DATA FIELD AFFECTED: 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A 1024-BIT EPROM EPROM STATUS BYTES ...
Page 6
... EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS1982 which is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS1982 that confirms proper receipt of the data ...
Page 7
... To execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS1982 and received back by the bus master are sent least significant bit first. ...
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... MEMORY FUNCTION FLOW CHART Figure DS1982 ...
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... MEMORY FUNCTION FLOW CHART (cont’d) Figure DS1982 ...
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... MEMORY FUNCTION FLOW CHART (cont’d) Figure DS1982 ...
Page 11
... Read Status command supplies an 8-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse. ...
Page 12
... EPROM data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS1982 until a Reset Pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a Reset Pulse ...
Page 13
... As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRC from the DS1982 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly ...
Page 14
... The bus master will issue the next byte of data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and the LSB of the new address ...
Page 15
... This command allows the bus master to read the DS1982’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS1982 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...
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... DS1982 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure DS1982 ...
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... ROM FUNCTIONS FLOW CHART Figure DS1982 ...
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... DS1982. During write time slots, the delay circuit determines when the DS1982 will sample the data line. For a read data time slot transmitted, the delay circuit determines how long the DS1982 will hold the data line low overriding the 1 generated by the master. If ...
Page 19
... CRC GENERATION The DS1982 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1982 to determine if the ROM data has been received error-free by the bus master. The equivalent ...
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... READ/WRITE TIMING DIAGRAM Figure 11 Write-1 Time Slot Write-0 Time Slot RESISTOR MASTER DS1982 < 120 s SLOT < LOW1 < REC < t < 120 s LOW0 SLOT < REC DS1982 + t should always RSTL R ...
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... Read-data Time Slot RESISTOR MASTER DS1982 PROGRAM PULSE TIMING DIAGRAM Figure < 120 s SLOT < LOWR 0 t < RELEASE < REC RDV t < DS1982 ...
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... REC t 480 RSTH t 480 RSTL t 15 PDHIGH t 60 PDLOW 480 DS1982 MAX UNITS NOTES + MAX UNITS NOTES 800 pF 9 MAX UNITS ...
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... The accumulative duration of the programming pulses for each address must not exceed 5 ms. and a maximum time slot of 120 after power has been applied the parasite capacitance will not affect may have to be reduced to as much as 0.5V to always ILMAX DS1982 resistor is used to ...