74cbtlv3126ds NXP Semiconductors, 74cbtlv3126ds Datasheet

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74cbtlv3126ds

Manufacturer Part Number
74cbtlv3126ds
Description
4-bit Bus Switch
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74CBTLV3126 provides a 4-bit high-speed bus switch with separate output enable
inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be
made with minimal propagation delay. The switch is disabled (high-impedance OFF-state)
when the output enable (nOE) input is LOW.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the GND through a pull-down resistor. The minimum value of the resistor is
determined by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
74CBTLV3126
4-bit bus switch
Rev. 01 — 5 January 2010
Supply voltage range from 2.3 V to 3.6 V
Standard ’126’-type pinout
High noise immunity
Complies with JEDEC standard:
ESD protection:
5 Ω switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
OFF
OFF
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 2.3 V to 3.6 V.
Product data sheet
OFF
.

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74cbtlv3126ds Summary of contents

Page 1

Rev. 01 — 5 January 2010 1. General description The 74CBTLV3126 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74CBTLV3126DS 74CBTLV3126PW −40 °C to +125 °C −40 °C to +125 °C 74CBTLV3126BQ [1] Also known as QSOP16. 4. Functional diagram 1OE 1A 2OE 2A 3OE 3A 4OE 4A 001aaj023 Fig 1. Logic symbol ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74CBTLV3126 n. 1OE 2 15 4OE 2OE 3OE GND 8 9 n.c. 001aal246 Fig 3. Pin configuration SOT519-1 (SSOP16) 5.2 Pin description Table 2. Pin description Symbol Pin SOT402-1 and SOT762-1 1OE to 4OE ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW I input clamping current IK I switch clamping current SK I switch current ...

Page 5

... NXP Semiconductors Table 6. Static characteristics …continued At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I ON-state V = 3.6 V; see S(ON) CC leakage current I power-off OFF I O leakage current supply current V = GND GND 3 ΔI additional pin nOE ...

Page 6

... NXP Semiconductors 9.2 ON resistance Table 7. Resistance recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions R ON resistance see Figure see Figure ...

Page 7

... NXP Semiconductors (Ω (1) 5 (2) (3) ( 0.5 1.0 1.5 = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 10. ON resistance as a function of input voltage 2 (Ω) 6 (1) (2) ( 125 °C. ...

Page 8

... NXP Semiconductors = 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 14. ON resistance as a function of input voltage; V 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter Conditions t propagation delay nA; ...

Page 9

... NXP Semiconductors 11. Waveforms Measurement points are given in Logic levels: V and V are typical output voltage levels that occur with the output load Fig 15. The data input (nA or nB) to output (nB or nA) propagation delays Table 9. Measurement points Supply voltage Input 2 2.7 V ...

Page 10

... NXP Semiconductors negative positive Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 17. Test circuit for measuring switching times Table 10 ...

Page 11

... NXP Semiconductors 12. Package outline SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 1.55 mm 1.73 0.25 0.10 1.40 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE ...

Page 12

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 3 0.2 0.00 0.18 2.9 Note 1 ...

Page 14

... NXP Semiconductors 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV3126_1 20100105 74CBTLV3126_1 Product data sheet ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 ON resistance test circuit and graphs Dynamic characteristics ...

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