74cbtlv3861pw NXP Semiconductors, 74cbtlv3861pw Datasheet
74cbtlv3861pw
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74cbtlv3861pw Summary of contents
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Rev. 2 — 20 January 2011 1. General description The 74CBTLV3861 is a 10-bit bus switch with one output enable (OE) input. When OE is LOW, the switch is closed and port A ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C SSOP24 74CBTLV3861DK 74CBTLV3861PW 40 C to +125 C TSSOP24 40 C to +125 C DHVQFN24 74CBTLV3861BQ [1] Also known as QSOP24 package 4. Functional diagram 23 OE Fig 1. Logic symbol Fig 2. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74CBTLV3861 n. A10 12 GND 001aan144 Fig 3. Pin configuration for TSSOP24 (SOT355-1) (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however soldered the solder land should remain floating or be connected to GND ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin n. A10 10, 11 GND B10 22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port Functional description [1] Table 3. Function selection Input [ HIGH voltage level LOW voltage level high-impedance OFF-state. ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate [1] Applies to control signal levels. 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 9.1 Test circuits GND GND and V = GND Fig 6. Test circuit for measuring OFF-state leakage current (one switch) 9.2 ON resistance Table 7. Resistance recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see ...
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... NXP Semiconductors 9.3 ON resistance test circuit and graphs GND Fig 8. Test circuit for measuring ON resistance (one switch (Ω (1) 5 (2) (3) ( 0.5 1.0 1.5 = 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = ...
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... NXP Semiconductors (Ω) 6 (1) (2) ( 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 12. ON resistance as a function of input voltage 3 125 C. (1) T amb = 85 C. (2) T amb = 25 C. ...
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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter Conditions t propagation delay An; pd see Figure enable time Bn; en see Figure disable time Bn; ...
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... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and V are typical output voltage levels that occur with the output load Fig 16. Enable and disable times 74CBTLV3861 Product data sheet ...
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... NXP Semiconductors negative positive Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 17. Test circuit for measuring switching times Table 10 ...
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... NXP Semiconductors 12. Package outline SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A UNIT max. 0.25 1.55 mm 1.73 0.25 0.10 1.40 0.0098 0.061 inches 0.068 0.01 0.0040 0.055 Note 1 ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 5 0.2 0.00 0.18 5.4 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV3861 v.2 20110120 • Modifications: Section 74CBTLV3861 v ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74CBTLV3861 Product data sheet 15 ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 ON resistance test circuit and graphs Dynamic characteristics ...