mm8203 Integrated Device Technology, mm8203 Datasheet - Page 4

• Manufacturer Part Number: mm8203
• Description: Cmos Oscillator
• Manufacturer: Integrated Device Technology

MM8203 Preliminary Data Sheet
MM8203 REVISION C DATE, 07/21/2010
Electrical Characteristics
VDD=2.25V to 2.75V, T
Notes 1. Measured with a 50Ω to GND termination
2: Measured at 48MHz output frequency
3. The MM8203 will support continuous VDD operation from 1.62 to 3.6V. The device can be powered up with a supply voltage at any of the 3 main supply rails of 1.8V, 2.5V or 3.3V.
4. Measured over 1000 cycles per JEDEC standard 65
5. Electrical parameters are guaranteed by design and characterization over the specified ambient operating temperature range, which is established when the device is mounted in a
test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
ElectroStaticDischa
Frequency Stability
Quiescent Current
Output HIGH level
Output LOW level
Output Frequency
Cycle-cycle Jitter
Input HIGH level
Input LOW level
Supply Voltage
Supply Current
Power-up time
Phase Noise
Period Jitter
Parameter
Duty Cycle
Rise Time
Fall Time
rge
A
=-40 to 85
Symbol
PJ
IDDQ
F
F
ESD
VDD
o
V
IDD
V
V
DC
V
RT
PN
FT
t
CJ
C unless otherwise noted. Typical values are measured at VDD=2.5V, T
OUT
TOT
on
RMS
OH
OL
IH
IL
Factory Programmable.Contact IDT for frequencies not listed
variation,aging (1st year at 35oC),shock&vibration. “ ” device
variation,aging (1st year at 35oC),shock&vibration. “I” device
Clock output duty cycle. Measured under 100MHz at VDD/2,
Clock output duty cycle. Measured over 100MHz at VDD/2,
Output valid time after VDD meets the specified range&CE
The absolute value of max change in the periods of any 2
Active supply current, VDD=2.5V, T=35oC, no output load
20% to 80% x VDD. Output load (C
80% to 20% x VDD. Output load (C
Total Frequency Stability over temperature,supply
Total Frequency Stability over temperature,supply
Human Body Model, tested per JESD D22-A114
5
Total RMS Period Jitter (including random and
[2.5V]
option, over -40-85
1MHz offset from carrier
option, over 0-70
CE=LOW, output disabled
adjacent cycles
Normal Operation
deterministic)
Conditions
I
I
OH
OL
transition
C
C
CE pin
CE pin
L
L
= -3mA
= 3mA
=7pF
=7pF
o
C range
o
1,2
1,2,4
C range
4
L
L
3
) =7pF, NSG-option
) =7pF, NSG-option
1,2
A
=35
o
C
VDD*0.7
VDD-0.4
4000
2.25
Min
-0.3
45
40
50
4
12,24,25,50
©2010 Integrated Device Technology, Inc.
2.25
-140
Typ
100
2.5
0.2
3.5
VDD+0.3
VDD*0.3
+2000
+2000
-135
Max
2.75
2.75
133
400
0.4
2.3
2.3
55
60
50
1
CMOS OSCILLATOR
dBc/Hz
ps
Units
MHz
ppm
ppm
mA
µA
ns
ns
µs
ps
%
%
V
V
V
V
V
V
RMS