nlsx3012 ON Semiconductor, nlsx3012 Datasheet - Page 9

• Manufacturer Part Number: nlsx3012
• Description: 2-bit 100 Mb/s Configurable Dual-supply Level Translator
• Manufacturer: ON Semiconductor

Level Translator Architecture
bi-directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, V
the input and output sides of the translator. When used to
transfer data from the V
referenced to the V
with a logic level matched to V
V
compatible to V
that independently determine the direction of the data flow
without requiring a directional pin. The one-shot circuits
are used to detect the rising or falling input signals. In
addition, the one shots decrease the rise and fall time of the
output signal for high-to-low and low-to-high transitions.
Input Driver Requirements
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi-directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent to in the opposite direction.
translator should be capable of driving 20 mA of peak
output current with an output impedance less than 25 W.
The bi-directional configuration of the translator results in
both input stages being active for a very short time period.
Although the peak current from the input signal circuit is
relatively large, the average current is small and consistent
with a standard CMOS input stage.
Output Load Requirements
Resistive pullup or pulldown loads of less than 50 kW
should not be used with this device. The NLSX3373 or
NLSX3378 open-drain auto sense translators are alternate
CC
The
The NLSX3012 consists of four bi-directional channels
Auto sense translators such as the NLSX3012 have a
For proper operation, the input driver to the auto sense
The NLSX3012 is designed to drive CMOS inputs.
to V
NLSX3012 auto sense translator provides
L
translation shifts input signals with a logic level
CC
L
L
to an output signal matched to V
and V
supply are translated to output signals
L
CC
to the V
, which set the logic levels on
CC
. In a similar manner, the
IMPORTANT APPLICATIONS INFORMATION
CC
ports, input signals
http://onsemi.com
L
.
NLSX3012
9
translator options for an application such as the I
requires pullup resistors.
Enable Input (EN)
tri-state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O V
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the V
Tolerant (OVT) protection.
Uni-Directional versus Bi-Directional Translation
uni-directional translator. One advantage of using the
translator as a uni-directional device is that each I/O pin
can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni-directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
or equal to the value of the V
sequencing of the power supplies will not damage the
device during the power up operation; however, the current
consumption of the device will increase if V
minus 0.4 V. In addition, the I/O V
in the high impedance state if either supply voltage is equal
to 0 V.
capacitors should be used on the V
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the power supply voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
The NLSX3012 has an Enable pin (EN) that provides
The NLSX3012 can function as a non-inverting
It is recommended that the V
For optimal performance, 0.01 to 0.1 mF decoupling
L
supply and has Over-Voltage
CC
L
supply should be less than
and I/O V
L
CC
CC
and V
and I/O V
minus 0.4 V. The
CC
L
L
power supply
pins to a high
exceeds V
2
C bus that
L
pins are
CC