93lc76ct-i-st Microchip Technology Inc., 93lc76ct-i-st Datasheet - Page 7

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93lc76ct-i-st

Manufacturer Part Number
93lc76ct-i-st
Description
8k Microwire Compatible Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet
2.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
FIGURE 2-2:
© 2007 Microchip Technology Inc.
CLK
DO
CS
DI
Erase All (ERAL)
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
High-Z
1
ERAL TIMING
0
0
1
0
x
•••
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (T
V
x
CC
Note:
T
must be ≥ 4.5V for proper operation of ERAL.
CSL
CSL
).
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
T
EC
T
SV
Check Status
Busy
Ready
DS21796J-page 7
High-Z
T
CZ

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