at93c46a-10ti-2.5 ATMEL Corporation, at93c46a-10ti-2.5 Datasheet - Page 6

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at93c46a-10ti-2.5

Manufacturer Part Number
at93c46a-10ti-2.5
Description
Three-wire Serial Eeprom 1k 64 X 16
Manufacturer
ATMEL Corporation
Datasheet
4. Timing Diagrams
Figure 4-1.
Note:
6
1. This is the minimum SK period.
AT93C46A
Synchronous Data Timing
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the ready/busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (t
valid only at V
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
Table 4-1.
CC
Organization Key for Timing Diagrams
I/O
D
A
N
N
= 5.0V ± 10%.
µ s
(1)
AT93C46A
x 16
D
A
15
5
CS
). The WRAL instruction is
0539L–SEEPR–11/07

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