at24c256b-10tu-1.8 ATMEL Corporation, at24c256b-10tu-1.8 Datasheet - Page 7

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at24c256b-10tu-1.8

Manufacturer Part Number
at24c256b-10tu-1.8
Description
Two-wire Serial Eeprom 256k 32,768 X 8
Manufacturer
ATMEL Corporation
Datasheet
Figure 4-3.
Figure 4-4.
Figure 4-5.
Note:
5279B–SEEPR–3/08
SCL
SDA
SDA OUT
SDA
SCL
SDA IN
1. The write cycle time t
SCL
WORDn
Software Reset
Bus Timing
Write Cycle Timing
Start bit
t
SU.STA
8th BIT
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
WR
1
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
t
ACK
HD.STA
t
t
F
LOW
2
t
AA
CONDITION
Dummy Clock Cycles
t
STOP
HIGH
3
t
HD.DAT
t
LOW
t
wr
8
(1)
t
t
SU.DAT
DH
CONDITION
9
START
Start bit
t
R
t
SU.STO
Stop bit
t
BUF
7

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