at24hc04b ATMEL Corporation, at24hc04b Datasheet - Page 7
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at24hc04b
Manufacturer Part Number
at24hc04b
Description
Two-wire Serial Eeprom 4k 512 X 8
Manufacturer
ATMEL Corporation
Datasheet
1.AT24HC04B.pdf
(21 pages)
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Figure 3-3.
Figure 3-4.
Figure 3-5.
Notes:
5227D–SEEPR–1/08
SCL
SDA
SDA
SCL
SDA OUT
SDA IN
1. The write cycle time t
SCL
WORDn
Software Reset
Bus Timing
Write Cycle Timing
Start bit
t
8th BIT
SU.STA
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b)
Clock nine cycles, (c) Create another start bit followed by stop bit condition as shown below. The
device is ready for next communication after above steps have been completed.
1
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
ACK
t
HD.STA
2
t
t
F
LOW
t
AA
CONDITION
Dummy Clock Cycles
STOP
3
t
HIGH
t
HD.DAT
t
LOW
t
8
wr
(1)
t
t
SU.DAT
DH
9
CONDITION
START
Start bit
t
R
t
SU.STO
Stop bit
t
BUF
7