at25f4096 ATMEL Corporation, at25f4096 Datasheet
at25f4096
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at25f4096 Summary of contents
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... The AT25F4096 provides 4,194,304 bits of serial reprogrammable Flash memory organized as 524,288 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25F4096 is available in a space-saving 8-lead EIAJ SOIC and 8- lead SAP packages. Table 1. Pin Configurations ...
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... Figure 1. Block Diagram AT25F4096 2 The AT25F4096 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. Block Write protection for top 1/8, top 1/4, top 1/2 or the entire memory array is enabled by programming the status register ...
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... MHz Open Read 3. MHz Open Write 2.7V 0°C to 70° 2.7V ≤ V ≤ -100 µA OH AT25F4096 = +3.6V (unless otherwise noted) CC Max Units +2.7V to +3.6V, CC Min Typ Max 2.7 3.6 10.0 17.0 15.0 45.0 2.0 10.0 -3.0 3.0 -3.0 3 ...
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... Byte Program Cycle Time BPC (2) Endurance Notes: 1. The programming time for n bytes will be equal This parameter is ensured by characterization at 3.0V, 25°C only. 3. One write cycle consists of erasing a sector, followed by programming the same sector. AT25F4096 4 = 40°C to +85°C, V – Min ...
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... WPEN bit in the status register is “0”. This will allow the user to install the AT25F4096 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “ ...
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... Figure 2. SPI Serial Interface AT25F4096 6 MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25F4096 SI SO SCK SCK SCK SCK CS 2454G–SFLSH–5/06 ...
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... The AT25F4096 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25F4096 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. ...
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... ATMEL), followed by the device code 64H. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of five levels of protection for the AT25F4096. The AT25F4096 is divided into eight sectors where the top 1/8, top quarter (1/4), top half (1/2), or all of the memory sectors can be protected (locked out) from write ...
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... High 1 Protected READ (READ): Reading the AT25F4096 via the SO (Serial Output) pin requires the fol- lowing sequence. After the CS line is pulled low to select a device, the Read instruction is transmitted via the SI line followed by the byte address to be read (Refer to Table 10). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the speci- fied address is then shifted out onto the SO line ...
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... Don’t Care Bits SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector which contains the byte must be erased. In order to erase the AT25F4096, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the Sector Erase instruction can be executed. ...
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... Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 3. Synchronous Data Timing CSS V IH SCK HI Figure 4. WREN Timing Figure 5. WRDI Timing 2454G–SFLSH–5/ VALID AT25F4096 CSH DIS HI-Z 11 ...
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... Figure 6. RDSR Timing SCK INSTRUCTION SI HIGH IMPEDANCE SO Figure 7. WRSR Timing Figure 8. READ Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO AT25F4096 MSB 3-BYTE ADDRESS ... ...
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... Figure 11. SECTOR ERASE Timing X = Don’t Care bit 2454G–SFLSH–5/ 3-BYTE ADDRESS AT25F4096 1st BYTE DATA-IN 256th BYTE DATA- ...
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... Figure 12. CHIP ERASE Timing CS SCK Don’t Care bit Figure 13. RDID Timing SCK HIGH IMPEDANCE SO AT25F4096 14 X HIGH IMPEDANCE MANUFACTURER CODE (ATMEL DATA OUT ...
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... Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8Y4 8-lead, 6. 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) –2.7 Low Voltage (2.7V to 3.6V) 2454G–SFLSH–5/06 Package 8S2 8Y4 Package Type Options AT25F4096 Operation Range Lead-Free/Halogen-Free/ Industrial Temperature (–40°C to 85°C) 15 ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT25F4096 ∅ End View ...
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... Colorado Springs, CO 80906 R 2454G–SFLSH–5/06 A PIN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.00 D 5.80 E 4.70 D1 2.85 E1 2. 0.50 TITLE 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP) Y4 AT25F4096 NOM MAX NOTE – 0.90 – 0.05 6.00 6.20 4.90 5.10 3.00 3.15 3.00 3.15 0.40 0.45 1.27 TYP 3.81 REF 0.60 0.70 DRAWING NO. 8Y4 5/24/04 REV ...
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... Revision History AT25F4096 18 Doc. Rev. Comments 2454G •Changed ordering part number from AT25F4096Y4-10YU-2.7 to AT25F4096Y4-10YH-2.7 •Added Note 1: “H” designates Green Package + RoHS Compliant, with NiPdAu Lead Finish to ordering information •Removed ‘Preliminary’ from all pages 2454G–SFLSH–5/06 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...