at88sa102s ATMEL Corporation, at88sa102s Datasheet - Page 12

• Manufacturer Part Number: at88sa102s
• Description: Cryptoauthentication
• Manufacturer: ATMEL Corporation

3.2.
3.3.
3.4.
12
The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to
exchange data with the host microprocessor. The PauseLong command includes an optional address field which is
compared to the values in Fuses 84-87. If the two match, then the chip enters the pause state, otherwise it continues to
monitor the bus for subsequent commands. The host would selectively put all but one AT88SA102S’s in the pause
state before executing the MAC command on the active chip. After the end of the watchdog interval all the chips will
have entered the sleep state and the selection process can be started with a wake token (which will then be honored
by all chips) and selection of a subsequent chip.
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the
following way:
IO Flow
The general IO flow for the MAC command is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Receive output block from the AT88SA102S, system checks CRC.
11. If CRC from the AT88SA102S is incorrect, indication transmission error, system resends Transmit flag.
12. System sends sleep flag to the AT88SA102S.
All commands other than MAC have a short execution delay. In these cases, the system should omit steps 6, 7 & 8
and replace this with a wait of duration t
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and CryptoAuthentication
will fall out of synchronization with each other. In order to speed recovery, CryptoAuthentication implements a timeout
that forces the chip to sleep.
AT88SA102S [Preliminary]
Byte
Number
0
1 to (N-2) Packet
N-1, N
System sends Wake token.
System sends Transmit flag.
Receive 0x11 value from the AT88SA102S to verify proper wakeup synchronization.
System sends Command flag.
System sends complete command block.
System waits t
System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the
computation engine is busy. If there was an error, the AT88SA102S responds with an error code.
System waits t
System sends Transmit flag.
Name
Count
Checksum
PARSE
EXEC
, refer to
for the AT88SA102S to check for command formation errors.
Meaning
Number of bytes to be transferred to the chip in the block, including count, packet and
checksum, so this byte should always have a value of (N+1). The maximum size block is
39 and the minimum size block is 4. Values outside this range will cause unpredictable
operation.
Command, parameters and data, or response. Refer to
details.
CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the
initial register value should be 0 and after the last bit of the count and packet have been
transmitted the internal CRC register should have a value that matches that in the block.
The first byte transmitted (N-1) is the least significant byte of the CRC value so the last
byte of the block is the most significant byte of the CRC.
Section
PARSE
3.1.1.
+ t
EXEC
.
Section 3.1.2
&
Section 4
8584A–SMEM–03/09
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