at49bv6416 ATMEL Corporation, at49bv6416 Datasheet - Page 12

• Manufacturer Part Number: at49bv6416
• Description: 64-megabit 4m X 16 Page Mode 2.7-volt Flash Memory
• Manufacturer: ATMEL Corporation

5. Command Definition Table
Notes:
12
Command Sequence
Read
Chip Erase
Plane Erase
Sector Erase
Word Program
Dual-Word Program
Enter Single-pulse Program
Mode
Single-pulse Word Program
Mode
Sector Softlock
Sector Unlock
Sector Hardlock
Erase/Program Suspend
Erase/Program Resume
Product ID Entry
Product ID Exit
Product ID Exit
Program Protection
Register – Block B
Lock Protection
Register – Block B
Status of Block B
Protection
Set Configuration Register
CFI Query
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages
5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.
6. PA is the plane address (A21 - A20).
7. During the fourth bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address
8. The fast programming option enables the user to program two words in parallel only when V
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
11. Any address within the user programmable register region. Please see
12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H.
13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H.
AT49BV6416(T)
each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
for details).
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H. PA (A21 - A20) must spec-
ify the same plane address as specified in the third bus cycle.
and Addr1, of the two words, D
purpose only.
(3)
(3)
(7)
(8)
Cycles
Bus
1
6
6
6
4
5
6
1
6
2
6
1
1
3
3
1
4
4
4
1
4
Addr
Addr
PA
Addr
X55
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
xxx
xxx
(6)
1st Bus
Cycle
D
Data
IN0
AA
AA
D
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
B0
FX
AA
30
98
OUT
IN
and D
AAA
Addr
SA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
IN1
2nd Bus
(4)
(2)
Cycle
, must only differ in address A0. This command should be used for manufacturing
Data
55
55
55
55
55
55
55
70
55
55
55
55
55
55
55
PA+00555
Addr
555
555
555
555
555
555
555
555
555
555
555
555
555
3rd Bus
Cycle
Data
A0
A1
C0
C0
E0
80
80
80
80
80
80
90
F0
90
“Protection Register Addressing Table” on page
xxxx
xxxx80
xxxx80
Addr0
Addr
Addr
555
555
555
555
555
555
(12)
xxx
8x
(12)
(13)
4th Bus
Cycle
(11)
00/01
D
Data
D
OUT
AA
AA
AA
D
AA
AA
AA
D
X0
IN0
IN
IN
(10)
(9)
PP
= 10V. The addresses, Addr0
Addr1
Addr
AAA
AAA
AAA
AAA
AAA
AAA
5th Bus
Cycle
Data
D
55
55
55
55
55
55
IN1
3451D–FLASH–04/06
SA
PA
SA
SA
Addr
555
555
(4)(5)
14
(6)
6th Bus
(4)
(4)
Cycle
-
17
Data
10
20
30
A0
40
60
13.