at49f8011 ATMEL Corporation, at49f8011 Datasheet - Page 5

• Manufacturer Part Number: at49f8011
• Description: 8-megabit 512k X 16/ 1m X 8 5-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

AT49F8011(T)
ERASE SUSPEND/ERASE RESUME: The erase suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual plane architecture, there is no need to use the
erase suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the erase suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane which contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the erase suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the erase
resume command. The erase resume command is a one bus cycle command that does
require the plane address which is determined by A18 - A16. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F8011(T) features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte/word loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. During a chip or sector erase opera-
tion, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. DATA polling may begin at any time during
the program cycle. Please see “Status Bit Table” for more details.
TOGGLE BIT: In addition to DATA polling the AT49F8011(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be used in conjunction with the toggle
bit which i s avai lable on I/O6. W hile a s ector i s eras e sus pended, a read or a
program operation from the suspended sector will result in the I/O2 bit toggling. Please see
“Status Bit Table” for more details.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open drain con-
nection allows for OR-tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49F8011(T) in the following ways: (a) V
sense: if V
is below 3.8V (typical), the
CC
CC
program function is inhibited. (b) V
power on delay: once V
has reached the V
sense
CC
CC
CC
level, the device will automatically time out 10 ms (typical) before programming. (c) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 4.5V to 5.5V power supply, the address inputs and
control inputs (OE, CE, and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
+ 0.6V.
CC
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