at49f4096 ATMEL Corporation, at49f4096 Datasheet - Page 4

• Manufacturer Part Number: at49f4096
• Description: At49f4096 4-megabit 256k X 16 5-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F4096 in
the following ways: (a) V
(typical), the program function is inhibited; (b) V
Command Definition (in Hex)
Notes:
Absolute Maximum Ratings*
4
Command
Sequence
Read
Chip Erase
Sector
Erase
Word
Program
Boot Block
Lockout
Product ID
Entry
Product ID
Exit
Product ID
Exit
Temperature Under Bias ................................ -55 C to +125 C
Storage Temperature ..................................... -65 C to +150 C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
(3)
(3)
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
(2)
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
together (from the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
Cycles
Bus
1
6
6
4
6
3
3
1
AT49F4096
Addr
5555
5555
5555
5555
5555
5555
Addr
xxxx
CC
1st Bus
Cycle
sense—if V
Data
D
AA
AA
AA
AA
AA
AA
F0
OUT
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
Addr
CC
(1)
2nd Bus
is below 3.8V
Cycle
CC
CC
Data
power on
55
55
55
55
55
55
+ 0.6V
Addr
5555
5555
5555
5555
5555
5555
3rd Bus
Cycle
delay—once V
device will automatically time out 10 ms (typical) before
programming; (c) Program inhibit—holding any one of OE
low, CE high or WE high inhibits program cycles; and
(d) Noise filter—pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
*NOTICE:
Data
A0
F0
80
80
80
90
Addr
5555
5555
5555
Addr
4th Bus
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Cycle
CC
Data
has reached the V
AA
AA
D
AA
IN
2AAA
2AAA
2AAA
Addr
5th Bus
Cycle
Data
55
55
55
CC
sense level, the
SA
Addr
5555
5555
(4)(5)
6th Bus
Cycle
Data
10
30
40