at49sn6416 ATMEL Corporation, at49sn6416 Datasheet
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
at49sn6416
Available stocks
Related parts for at49sn6416
at49sn6416 Summary of contents
Page 1
... Common Flash Interface (CFI) 1. Description The AT49SN6416( 1.8-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 1.8V power supply, making it ideally suited for In-System programming. The device can be configured to operate in the asynchronous/page read (default mode) or burst read mode ...
Page 2
... A0 - A21 AVD CLK RESET WP VPP WAIT VCCQ NC 2.1 56-ball CBGA (Top View) AT49SN6416(T) 2 Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection and Power Supply for Accelerated Program Operations WAIT ...
Page 3
... Latency versus Input Clock Frequency” page 21. The “Burst Read Waveform” Figure page 32. The clock latency is not affected by the value of the B9 bit. The AT49SN6416(T) as shown on page 32 illustrates a clock 8-1). The Hold Data for 2 Clock Cycles Read page 21. The default state (after power-up or page 21 ...
Page 4
... AVD is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from the device for a burst operation. After the clock latency cycles, the data at the next burst address location is read for each following clock cycle. Figure 3-1. AT49SN6416(T) 4 page 30. Word Boundary ...
Page 5
... When operating in the linear burst read mode ( with the 3-1). The delay takes place only once, and only if the burst sequence crosses a on page 33 AT49SN6416(T) Table 3-1). The delay Output Delay Hold Data for 2 Clock Cycles Clock Cycle 4 Clock Cycles 6 Clock Cycles 32, the valid address is latched at point A ...
Page 6
... The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. AT49SN6416( resume the burst access reasserted and the CLK is restarted. ...
Page 7
... Flexible Sector Protection The AT49SN6416(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. ...
Page 8
... Table 3- Figure 3-2. Note: AT49SN6416(T) 8 Hardlock and Softlock Protection Configurations in Conjunction with WP Hard- Soft- WP lock lock Sector Locking State Diagram UNLOCKED ...
Page 9
... WSM was successful in performing the preferred operation (see 3464C–FLASH–2/05 Sector Protection Status I/O0 Sector Protection Status 0 0 Sector Not Locked 0 1 Softlock Enabled 1 0 Hardlock Enabled 1 1 Both Hardlock and Softlock Enabled Table 3-4). AT49SN6416(T) 9 ...
Page 10
... Figure 3-3. Read Status Register in the Burst Mode CLK CE OE AVD A21 XX 40H/10H I/O0 - I/O15 (1) WAIT Note: 1. The WAIT signal is for a burst configuration setting of B10 and AT49SN6416( ADDRESS DATA 70H B 00H 80H 3464C–FLASH–2/05 ...
Page 11
... Program Resume command is issued Program or Erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. Indicates program or erase status of the addressed plane. AT49SN6416(T) PSS SLS 2 1 Notes ...
Page 12
... Resume are valid commands during a Program Suspend. 3.17 128-bit Protection Register The AT49SN6416(T) contains a 128-bit register that can be used for security purposes in sys- tem design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number ...
Page 13
... Hardware Data Protection Hardware features protect against inadvertent programs to the AT49SN6416(T) in the following ways: (a) V erase functions are inhibited. (b) V level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles ...
Page 14
... Full Status Check Flowchart Read Status Register 1 SR3 = 0 1 SR4 = 0 1 SR1 = Protect Error 0 Program Successful AT49SN6416(T) 14 3.23 Bus Operation Write Write Read Program Suspend Loop Idle No Yes Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations ...
Page 15
... Status) within the Same Plane 3464C–FLASH–2/05 3.27 Operation Program Completed (Read Write FF Array) Read Data If the Suspend Plane was placed in Read mode: AT49SN6416(T) Program Suspend/Resume Procedure Bus Command Comments Data = B0 Program Write Addr = Sector address to Suspend Suspend (SA) Data = 70 Read Write ...
Page 16
... Program? Program Read No Loop Done? Yes Write D0, (Erase Resume) Any Address Erase Resumed Write 70H Any Address (Read Status) within the Same Plane AT49SN6416(T) 16 3.29 Bus Operation Write Write Read Erase Completed Idle Idle Write Read or (Read Array) Write FF Write Read Array ...
Page 17
... SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5 error is detected, clear the status register before attempting an erase retry or other error recovery. AT49SN6416(T) Sector Erase Procedure Bus Command Comments Sector ...
Page 18
... SR1, SR4 = Program Error Register Locked; = SR1, SR4 Program Aborted 0 Program Successful AT49SN6416(T) 18 3.35 Bus Operation Write Write Read Idle Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. ...
Page 19
... During the second bus sycle, the manufacturer code is read from address PA+00000H, the device code is read from address PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H (AT49SN6416) or addresses 3F8081H - 3F8088H (AT49SN6416T). 12. The plane address should be the same during the first and second bus cycle. ...
Page 20
... User B Notes: 1. For the AT49SN6416, all address lines not specified in the above table, A21 - A8, must be 0 when accessing the Protection Register. 2. For the AT49SN6416T, all address lines not specified in the above table, A21 - A8, must be 3F80H when accessing the Protection Register. AT49SN6416(T) ...
Page 21
... Burst Configuration Register Table B15 Program (AT49SN6416) B15 Program (AT49SN6416T) B15 Read B14 (2) B13 - B11: B10 Notes: 1. Default State 2. Burst configuration setting of B13 - B11 = 010 (clock latency of two (hold data for two clock cycles) and (WAIT asserted one clock cycle before data is valid) is not supported. ...
Page 22
... Linear 0 1 0-1-2 1-2-3 2-3-4 3-4-5 ... ... AT49SN6416(T) 22 Burst Addressing Sequence (Decimal) 8-word Burst Length B2 – 010 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 16-word Burst Length Continuous Burst B2 – 011 B2 – 111 Linear Linear 0-1-2...14-15 0-1-2-3-4-5-6... 1-2-3...15-16 1-2-3-4-5-6-7... 2-3-4...16-17 2-3-4-5-6-7-8... 3-4-5...17-18 3-4-5-6-7-8-9 ...
Page 23
... A8000 - AFFFF B B0000 - B7FFF B B8000 - BFFFF B C0000 - C7FFF B C8000 - CFFFF B D0000 - D7FFF B D8000 - DFFFF B E0000 - E7FFF C AT49SN6416(T) AT49SN6416 (Continued) Sector Size (Words) Address Range (A21 - A0) SA36 32K SA37 32K SA38 32K SA39 32K 100000 - 107FFF SA40 32K 108000 - 10FFFF SA41 32K ...
Page 24
... Memory Organization – AT49SN6416 (Continued) Plane Sector Size (Words) C SA72 32K C SA73 32K C SA74 32K C SA75 32K C SA76 32K C SA77 32K C SA78 32K C SA79 32K C SA80 32K C SA81 32K C SA82 32K C SA83 32K C SA84 32K C SA85 32K C SA86 32K C SA87 32K ...
Page 25
... D8000 - DFFFF B E0000 - E7FFF B E8000 - EFFFF B F0000 - F7FFF B F8000 - FFFFF B 100000 - 107FFF B 108000 - 10FFFF B 110000 - 117FFF B 118000 - 11FFFF AT49SN6416(T) AT49SN6416T (Continued) Sector Size (Words) Address Range (A21 - A0) SA36 32K SA37 32K SA38 32K SA39 32K SA40 32K SA41 32K SA42 32K ...
Page 26
... Memory Organization – AT49SN6416T (Continued) Plane Sector Size (Words) B SA72 32K B SA73 32K B SA74 32K B SA75 32K B SA76 32K B SA77 32K B SA78 32K B SA79 32K B SA80 32K B SA81 32K B SA82 32K B SA83 32K B SA84 32K B SA85 32K B SA86 32K B SA87 32K ...
Page 27
... X Output Disable X Reset X Product Identification Software Notes can be VIL or VIH. 2. Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00DE - AT49SN6416; 00D8H - AT49SN6416T. 4. The VPP pin can be tied (min) = 0.9V. IHPP 6. V (max) = 0.4V. ILPP 3464C–FLASH–2/05 Industrial (4) WE ...
Page 28
... CC 15. Input Test Waveforms and Measurement Level 16. Output Test Load 17. Pin Capacitance ( MHz 25°C Typ OUT Note: 1. This parameter is characterized and is not 100% tested. AT49SN6416(T) 28 Condition I 0. CCQ MHz OUT MHz ...
Page 29
... ADDRESS VALID ACC2 t RESET RO HIGH Z I/O0 - I/O15 - t after the address transition without impact on t ACC after the falling edge of CE without impact AT49SN6416(T) Min Max 150 (1)( OUTPUT VALID ...
Page 30
... After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable. 23. Page Read Cycle Waveform 2 CE I/O0-I/O15 A2 -A21 A0 -A1 (1) AVD OE RESET Note: 1. AVD may remain low as long as the page address is stable. AT49SN6416( DATA VALID t ACC2 t AAV t AHAV t PAA t ACC2 t AAV t AHAV ...
Page 31
... B10 = 1 and After the high-to-low transition on AVD, AVD may remain low. 3464C–FLASH–2/05 t CLK ... t AHCK t CECK CESAV t CKAV t AHAV t t AAV QHCK ... D14 D3 D4 AT49SN6416(T) Min Max 3.5 3 CKH ... ... t ...
Page 32
... Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 4) AVD CLK A0-A21 I/O0-I/O15 (1) WAIT Note: 1. The Dashed line reflects a burst configuration register setting of B10 and Solid line reflects a burst configura- tion register setting of B10 = 0, B8 and AT49SN6416( D11 D12 D13 D14 D9 D10 D11 ...
Page 33
... B10 = 1 and During Burst Suspend, CLK signal can be held low or high. 3464C–FLASH–2/ VALID D0 t CLK ... t AHCK CKAV t AHAV t t AAV QHCK AT49SN6416( HIGH Z t CKH t CKL t t CKQV CEQZ ...
Page 34
... After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. (1) 31.2 CE Controlled WE I/O0-I/O15 A0 -A21 AVD CE Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. AT49SN6416(T) 34 DATA VALID t AAV t AHAV AVLP t WP DATA VALID t AAV t AHAV ...
Page 35
... WE Controlled CE I/O0 - I/O15 A0 - A21 WE AVD Note: 1. The CLK input should not toggle. (1) 33.2 CE Controlled WE I/O0 - I/O15 A0 - A21 CE AVD Note: 1. The CLK input should not toggle. 3464C–FLASH–2/05 AT49SN6416(T) Min Max DATA VALID V IL DATA VALID V IL Units ...
Page 36
... For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H. AT49SN6416(T) 36 PROGRAM CYCLE t ...
Page 37
... Z = 256 (Top); 8K bytes (Bottom) 007Eh 8K bytes (Top); 64K bytes 126 (Bottom) 0000h 8K bytes (Top); 64K bytes 126 (Bottom) 0000h 8K bytes (Top);64K bytes 256 (Bottom) 0001h 8K bytes (Top);64K bytes 256 (Bottom) AT49SN6416(T) 37 ...
Page 38
... AT49SN6416(T) 38 AT49SN6416 Comments VENDOR SPECIFIC EXTENDED QUERY 0050h “P” 0052h “R” 0049h “I” 0031h Major version number, ASCII 0030h Minor version number, ASCII Bit 0 – chip erase supported, 0 – no, 1 – yes Bit 1 – ...
Page 39
... CC t ACC (ns) Active Standby 70 30 0.035 70 30 0.035 56C2 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 3464C–FLASH–2/05 Ordering Code Package AT49SN6416-70CI 56C2 AT49SN6416T-70CI 56C2 Package Type AT49SN6416(T) Operation Range Industrial (-40° to 85°C) Industrial (-40° to 85°C) 39 ...
Page 40
... Bottom View 2325 Orchard Parkway San Jose, CA 95131 R AT49SN6416( 2.75 mm Ref Øb TITLE 56C2, 56-ball ( Array 1.0 mm Body, 0.75 mm Ball Pitch Ceramic Ball Grid Array Package (CBGA) 0. Seating Plane Side View A1 ...
Page 41
... Changed the I spec to 35 µA. SB1 • Modified note 11 and added note 12 on • Modified note 1 and added note 2 on • Modified the B15 section in the “Burst Configuration Register Table” on page 21 AT49SN6416(T) 33 were changed such 21 and 22. page 19. page 20. 41 ...
Page 42
... Atmel Corporation 2005. All rights reserved. Atmel SM Everywhere You Are and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...