is62wv1288bll-55tl Integrated Silicon Solution, Inc., is62wv1288bll-55tl Datasheet - Page 8

• Manufacturer Part Number: is62wv1288bll-55tl
• Description: 128k X 8 Low Voltage, Ultra Low Power Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS62WV1288ALL, IS62WV1288BLL
8
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
Symbol
ADDRESS
t
t
t
t
t
t
t
t
t
t
V
go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Wc
scs1/
AW
hA
sA
PWe
sd
hd
hzWe
LzWe
dd
-0.2V/V
(3)
t
(3)
DOUT
scs2
CS1
CS2
DIN
WE
dd
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-0.3V and output loading specified in Figure 1.
t
DATA UNDEFINED
SA
Integrated Silicon Solution, Inc. — www.issi.com —
t
Min.
AW
45
35
35
20
—
35
0
0
5
0
t
45 ns
HZWE
t
t
Max.
SCS2
SCS1
—
—
—
—
—
—
—
—
20
—
t
WC
t
PWE
(1,2)
HIGH-Z
(Over Operating Range)
Min. Max.
45
45
40
25
—
t
55
0
0
0
5
SD
55 ns
DATA-IN VALID
—
—
—
—
—
—
—
—
20
—
t
HA
t
t
LZWE
HD
Min. Max.
50
30
—
0
0
0
5
70
60
60
70 ns
20
—
—
—
—
—
—
—
—
—
1-800-379-4774
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
04/02/08
Rev. D