is62c5128bl Integrated Silicon Solution, Inc., is62c5128bl Datasheet

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is62c5128bl

Manufacturer Part Number
is62c5128bl
Description
512k?x?8?high-speed?cmos?static?ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
IS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns
• Low Active Power: 50 mW (typical)
• Low Standby Power: 10 mW (typical)
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
• Available in 32-pin sTSOP-I, 32-pin SOP and
• Commercial, Industrial and Automotive tem-
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
09/15/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
CMOS standby
required
32-pin TSOP-II packages
perature ranges available
I/O0-I/O7
A0-A18
V
GND
DD
WE
OE
CE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
4,194,304-bit static RAMs organized as 524,288 words by
8 bits. They are fabricated using
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times as
fast as 45ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62C5128BL and IS65C5128BL are packaged in the
JEDEC standard 32-pin sTSOP-I, 32-pin SOP and 32-pin
TSOP-II packages
ISSI
IS62C5128BL and IS65C5128BL are high-speed,
MEMORY ARRAY
COLUMN I/O
512K X 8
SEPTEMBER 2010
ISSI
's high-performance
1

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is62c5128bl Summary of contents

Page 1

... IS62C5128BL, IS65C5128BL 512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 45ns • Low Active Power (typical) • Low Standby Power (typical) CMOS standby • TTL compatible interface levels • Single 5V ± 10% power supply • Fully static operation: no clock or refresh required • Available in 32-pin sTSOP-I, 32-pin SOP and 32-pin TSOP-II packages • Commercial, Industrial and Automotive tem- perature ranges available • ...

Page 2

... IS62C5128BL, IS65C5128BL  PIN CONFIGURATION 32-pin sTSOP (TYPE I)  A11 A13 A18 6 A15 A17 9 A16 10 A14 11 A12 PIN DESCRIPTIONS A0-A18 Address Inputs CE Chip Enable 1 Input OE Output Enable Input Write Enable Input WE I/O0-I/O7 I nput/Output V Power dd GND Ground 2 32-pin  ...

Page 3

... IS62C5128BL, IS65C5128BL  TRUTH TABLE         Mode  WE  CE    Not Selected X Output Disabled H Read H Write L ABSOLUTE MAXIMUM RATINGS   Symbol  Parameter    V Terminal Voltage with Respect to GND term t Storage Temperature stg P Power Dissipation Output Current (LOW) out Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 4

... IS62C5128BL, IS65C5128BL  OPERATING RANGE   Range  Ambient Temperature  Commercial 0°C to +70°C Industrial -40°C to +85°C   Automotive -40°C to +125°C POWER SUPPLY CHARACTERISTICS     Symbol Parameter  Test Conditions  i Average operating Current i out Dynamic Operating V = Max ...

Page 5

... IS62C5128BL, IS65C5128BL  READ CYCLE SWITCHING CHARACTERISTICS     Symbol  Parameter  t Read Cycle Time rC t Address Access Time aa t Output Hold Time oha t CE Access Time aCe t OE Access Time doe High-Z Output (2) hzoe t ( Low-Z Output lzoe t ( High-Z Output hzCe t ( Low-Z Output lzCe Notes: 1. Test conditions assume signal transition times less, timing reference levels of 1.5V, input pulse levels 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ± ...

Page 6

... IS62C5128BL, IS65C5128BL  AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCS HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions OHA DOE ...

Page 7

... IS62C5128BL, IS65C5128BL  WRITE CYCLE SWITCHING CHARACTERISTICS     Symbol  Parameter  t Write Cycle Time Write End sCe t Address Setup Time aw to Write End t Address Hold from Write End ha t Address Setup Time Pulse Width (OE =High) 1 Pwe t WE Pulse Width (OE=Low) 2 Pwe t Data Setup to Write End sd t Data Hold from Write End LOW to High-Z Output (2) hzwe t (2) WE HIGH to Low-Z Output lzwe Notes: 1 ...

Page 8

... IS62C5128BL, IS65C5128BL  AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled) ADDRESS DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state (1, VALID ADDRESS t SCS ...

Page 9

... IS62C5128BL, IS65C5128BL  WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ADDRESS OE LOW CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...

Page 10

... IS62C5128BL, IS65C5128BL  DATA RETENTION SWITCHING CHARACTERISTICS   Symbol  Parameter  for Data Retention Data Retention Current dr t Data Retention Setup Time See Data Retention Waveform sdr t Recovery Time rdr Note:  1. Typical Values are measured 5V DATA RETENTION WAVEFORM (CE Controlled) t VDD 4. GND 10 Test Condition  See Data Retention Waveform V = 2.0V, CE ≥ V – ...

Page 11

... IS62C5128BL, IS65C5128BL  ORDERING INFORMATION Industrial Range: –40°C to +85°C   Speed (ns)  Order Part No.  45 IS62C5128BL-45QI IS62C5128BL-45QLI IS62C5128BL-45HI IS62C5128BL-45HLI IS62C5128BL-45TI IS62C5128BL-45TLI Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 09/15/2010 Package 450-mil Plastic SOP 450-mil Plastic SOP, Lead-free 32-pin STSOP-I ...

Page 12

... IS62C5128BL, IS65C5128BL  12 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 09/15/2010 ...

Page 13

... IS62C5128BL, IS65C5128BL  Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 09/15/2010 13 ...

Page 14

... IS62C5128BL, IS65C5128BL  14 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 09/15/2010 ...

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