is42s16160a1-7t Integrated Silicon Solution, Inc., is42s16160a1-7t Datasheet - Page 13

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is42s16160a1-7t

Manufacturer Part Number
is42s16160a1-7t
Description
256 Mb Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
IS42S83200A1
IS42S16160A1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
POWER ON SEQUENCE
Before starting normal operation, the following
power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain
2. Maintain stable power, stable clock, and NOP
3. Issue precharge commands for all banks. (PRE
4. After all banks become idle state (after tRP),
5. Issue a mode register set command to initialize
After these sequence, the SDRAM is idle state and
ready for normal operation.
LATENCY
CKE high, DQM high and NOP condition at the
inputs.
input conditions for a minimum of 200µs.
or PREA)
issue 8 or more auto-refresh commands.
the mode register.
MODE
BA0 BA1 A12 A11 A10 A9
0
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CL
0
R: Reserved for Future Use
0
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
SW
/CAS LATENCY
0
SW
0
1
R
R
2
3
R
R
R
R
A8 A7
0
Burst Write
Single Write
0
A6
LTMODE
A5 A4
A3
BT
LENGTH
BURST
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can
be programmed by setting the mode register
(MRS). The mode register stores these data until
the next MRS command, which may be issued
when all banks are in idle state. After tRSC from a
MRS command, the SDRAM is ready for new
command.
BURST
TYPE
A2 A1
BL
BA0,1 A12-A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
0
1
A0
CLK
/CS
/RAS
/CAS
/WE
Full Page
BT=0
SEQUENTIAL
INTERLEAVED
1
2
4
8
R
R
R
V
BT=1
1
2
4
8
R
R
R
R
ISSI
13
®

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