is42s16160c-7tli Integrated Silicon Solution, Inc., is42s16160c-7tli Datasheet

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... IS42S83200C is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and IS42S16160C and IC42S16160C is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. IS42S83200C, IS42S16160C and IC42S16160C achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. ...

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... IS42S83200C IS42S16160C, IC42S16160C CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O 2 DQM : Output Disable / Write Mask A0-12 : Address Input BA0,1 : Bank Address Vdd : Power Supply VddQ : Power Supply for Output ...

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... IS42S83200C IS42S16160C, IC42S16160C Note: This figure shows the IS42S83200C. The IS42S16160C and IC42S16160C configuration is 8192x512x16 of cell array and DQ0-15 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 3 ...

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... IS42S83200C IS42S16160C, IC42S16160C Pin Descriptions SYMBOL TYPE Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CLK Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the ...

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... IS42S83200C IS42S16160C, IC42S16160C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

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... IS42S83200C IS42S16160C, IC42S16160C DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter Symbol Operating Current I CC1 (One Bank Active Precharge Standby CC2 Current in power-down mode I PS CC2 I N Precharge Standby CC2 Current in non power-down mode I NS CC2 I P Active Standby CC3 ...

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... IS42S83200C IS42S16160C, IC42S16160C AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/ 3.3V, Commerical grade Industrial grade:T ...

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... IS42S83200C IS42S16160C, IC42S16160C OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to active delay Last data in to new col. address delay ...

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... IS42S83200C IS42S16160C, IC42S16160C AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width ...

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... IS42S83200C IS42S16160C, IC42S16160C TRUTH TABLE Command Truth Table COMMAND Symbol Device deselect DSL No operation NOP Burst stop BST Read RD Read with auto precharge RDA Write WR Write with auto precharge WRA Bank activate ACT Precharge select bank PRE Precharge all banks PALL ...

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... IS42S83200C IS42S16160C, IC42S16160C Function Truth Table Current state /CS /RAS /CAS Idle Row active ...

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... IS42S83200C IS42S16160C, IC42S16160C Current state /CS /RAS Precharging Row activating Write H X recovering Write H X recovering with ...

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... IS42S83200C IS42S16160C, IC42S16160C Notes: 1. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 2. Illegal if tRCD is not satisfied. 3. Illegal if tRAS is not satisfied. 4. Must satisfy burst interrupt condition. 5. Must satisfy bus contention, bus turn around, and/or write recovery requirements. ...

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... IS42S83200C IS42S16160C, IC42S16160C A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address BA0 BA1 A12 Function Normal MRS Mode CAS Latency Latency Reserved Reserved Reserved ...

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... IS42S83200C IS42S16160C, IC42S16160C Power-up sequence Power-up sequence The SDRAM should be goes on the following sequence with power up. The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence. ...

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... IS42S83200C IS42S16160C, IC42S16160C Operation of the SDRAM Read/Write Operations Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input ...

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... IS42S83200C IS42S16160C, IC42S16160C Write operation Burst write or single write mode is selected 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set and 8, like burst read operations ...

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... IS42S83200C IS42S16160C, IC42S16160C Auto Precharge Read with auto-precharge In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is required before execution of the next command ...

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... IS42S83200C IS42S16160C, IC42S16160C Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command. During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command. Integrated Silicon Solution, Inc. — ...

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... IS42S83200C IS42S16160C, IC42S16160C Command Intervals Read command to Read command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. ...

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... IS42S83200C IS42S16160C, IC42S16160C Write command to Write command interval 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed ...

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... IS42S83200C IS42S16160C, IC42S16160C Read command to Write command interval 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input. 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed ...

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... IS42S83200C IS42S16160C, IC42S16160C Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed ...

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... IS42S83200C IS42S16160C, IC42S16160C Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid ...

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... IS42S83200C IS42S16160C, IC42S16160C Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command ...

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... IS42S83200C IS42S16160C, IC42S16160C Read command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read ...

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... IS42S83200C IS42S16160C, IC42S16160C Write command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of UDQM and LDQM for assurance of the clock defined by tDPL. Integrated Silicon Solution, Inc. — ...

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... IS42S83200C IS42S16160C, IC42S16160C Bank active command interval 1. Same bank: The interval between the two bank active commands must be no less than tRC the case of different bank active commands: The interval between the two bank active commands must be no less than tRRD ...

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... IS42S83200C IS42S16160C, IC42S16160C DQM Control The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and LDQM is different during reading and writing. Reading When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low, the output buffer becomes Low-Z, enabling data output ...

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... IS42S83200C IS42S16160C, IC42S16160C Refresh Auto-refresh All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.). ...

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... IS42S83200C IS42S16160C, IC42S16160C Timing Waveforms Read Cycle Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 31 ...

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... IS42S83200C IS42S16160C, IC42S16160C Write Cycle 32 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 ...

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... IS42S83200C IS42S16160C, IC42S16160C Mode Register Set Cycle Read Cycle/Write Cycle Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 33 ...

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... IS42S83200C IS42S16160C, IC42S16160C Read/Single Write Cycle 34 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 ...

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... IS42S83200C IS42S16160C, IC42S16160C Read/Burst Write Cycle Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 35 ...

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... IS42S83200C IS42S16160C, IC42S16160C Auto Refresh Cycle Self Refresh Cycle 36 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 ...

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... IS42S83200C IS42S16160C, IC42S16160C Clock Suspend Mode Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 37 ...

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... IS42S83200C IS42S16160C, IC42S16160C Power Down Mode Initialization Sequence 38 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/08 ...

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... MHz 7 IC42S16160C-7TL 133 MHz 7.5 IC42S16160C-75TL o Industrial Range: - +85 Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S16160C-7TLI 133 MHz 7.5 IS42S16160C-75TLI Integrated Silicon Solution, Inc. — www.issi.com Rev. A 12/05/ Package 54-pin TSOP-II, Lead-free 54-pin TSOP-II, Lead-free 54-pin TSOP-II, Lead-free Package 54-pin TSOP-II, Lead-free ...

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... C 0.12 0.21 D 22.02 22.42 E1 10.03 10.29 E 11.56 11.96 e 0.80 BSC L 0.40 0.60 L1 — — — ZD 0.71 REF 0° 8° Integrated Silicon Solution, Inc. Rev. D 03/13/07 N/2 Inches Min Max Symbol Ref. Std. No. Leads (N) 0.047 0.002 0.006 — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — ...