is42s16100c1 Integrated Silicon Solution, Inc., is42s16100c1 Datasheet
is42s16100c1
Manufacturer Part Number
is42s16100c1
Description
512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42S16100C1.pdf
(81 pages)
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PIN DESCRIPTIONS
IS42S16100C1
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
• Two banks can be operated simultaneously and
• Dual internal bank controlled by A11
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and
• Byte controlled by LDQM and UDQM
• Industrial temperature up to 143 MHz
• Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
• Lead-free package option
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. D
11/03/06
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
A0-A11
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
positive clock edge
independently
(bank select)
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
precharge command
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
1-800-379-4774
DESCRIPTION
ISSI
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
CAS
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
’s 16Mb Synchronous DRAM IS42S16100C1 is
GNDQ
GNDQ
VDDQ
VDDQ
LDQM
DQ7
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
CAS
RAS
VDD
A11
A10
WE
CS
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
NOVEMBER 2006
ISSI
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
IDQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
®
1
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