is42s16400b1 Integrated Silicon Solution, Inc., is42s16400b1 Datasheet - Page 18

• Manufacturer Part Number: is42s16400b1
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram - Integrated Silicon Solution, Inc
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16400B1
CAS Latency
18
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid
by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as shown
in CAS Latency diagrams. The Allowable Operating
Frequency table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
xx x x
CAS Latency - 2
Integrated Silicon Solution, Inc. — www.issi.com —
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
xx
xx
CAS Latency
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
Speed
NOP
NOP
T2
T2
Allowable Operating Frequency (MHz)
7
D
OUT
t
t
OH
LZ
t
AC
x
x
x
x
NOP
T3
T3
CAS Latency = 2
D
DON'T CARE
UNDEFINED
OUT
t
OH
100
T4
CAS Latency = 3
ISSI
1-800-379-4774
133
12/09/03
Rev. A
®