is42s32160c Integrated Silicon Solution, Inc., is42s32160c Datasheet - Page 13

• Manufacturer Part Number: is42s32160c
• Description: 16mx32 512mb Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

I
IS42S32160C
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/22/09
(iv) WRITE with Auto Precharge Interrupted by a WRITE
(iii) WRITE with Auto Precharge Interrupted by a READ
Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when
when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m
is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m.
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
COMMAND
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
NOP
T0
Page Active
T0
NOP
WRITE - AP
BANK n,
Page Active
BANK n
COL a
D
T1
WRITE - AP
a
IN
BANK n,
WRITE with Burst of 4
Page Active
BANK n
COL a
T1
D
a
IN
WRITE with Burst of 4
T2
a + 1
D
NOP
IN
a + 1
T2
D
NOP
IN
a + 2
T3
D
IN
BANK m,
READ - AP
T3
COL d
BANK m
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
Interrupt Burst, Write-Back
t
d
IN
WR - BANK n
T4
WRITE with Burst of 4
NOP
T5
d + 1
NOP
D
T5
IN
NOP
Precharge
t
RP - BANK n
T6
d + 2
NOP
Precharge
D
t RP - BANK n
IN
T6
D
NOP
OUT
d
DON’T CARE
DON’T CARE
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
T7
d + 1
D
NOP
t RP - BANK m
OUT
I
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