m24c04-w STMicroelectronics, m24c04-w Datasheet - Page 13

• Manufacturer Part Number: m24c04-w
• Description: 16kbit, 8kbit, 4kbit, 2kbit And 1kbit Serial I2c Bus Eeprom
• Manufacturer: STMicroelectronics

M24C16, M24C08, M24C04, M24C02, M24C01
3.6
3.6.1
Figure 6.
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High (during
the period from the Start condition until the end of the address byte), the device replies to
the data byte with NoAck, as shown in
the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
Write mode sequences with WC = 1 (data write inhibited)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
Figure
6, and the location is not modified. If, instead,
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
Figure
DATA IN 2
Figure
7, and waits for an
NO ACK
Device operation
7.
DATA IN 3
AI02803C
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