m24c32-f STMicroelectronics, m24c32-f Datasheet - Page 18

• Manufacturer Part Number: m24c32-f
• Description: 128 Kbit, 64 Kbit And 32 Kbit Serial I?c Bus Eeprom
• Manufacturer: STMicroelectronics

Device operation
4.10
18/38
Figure 9.
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
sequence can be used by the bus master.
The sequence, as shown in
1.
2.
3.
First byte of instruction
with RW = 0 already
decoded by the device
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table 17
Write cycle polling flowchart using ACK
and
ReStart
Stop
Table 18
NO
Figure
, but the typical time is shorter. To make use of this, a polling
NO
Start condition
Device select
addressing the
with RW = 0
in progress
operation is
Write cycle
Returned
9, is:
memory
ACK
Next
YES
Write operation
Write operation
Continue the
Data for the
YES
NO
and receive ACK
Send address
condition
Start
M24128, M24C64, M24C32
Random Read operation
Device select
Continue the
with RW = 1
YES
AI01847d
w
) is