m24c32-df STMicroelectronics, m24c32-df Datasheet - Page 6
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m24c32-df
Manufacturer Part Number
m24c32-df
Description
32 Kbit Serial I2c Bus Eeprom
Manufacturer
STMicroelectronics
Datasheet
1.M24C32-DF.pdf
(42 pages)
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Description
M24C32-x and M24C32-DF devices are I2C-compatible electrically erasable programmable
memories (EEPROM). They are organized as 8192 × 8 bits.
The M24C32-D also offers an additional page, named the Identification Page (32 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
Figure 1.
The device behaves as a slave in the I2C-bus protocol, with all memory operations
synchronized by the serial clock. Read and Write operations are initiated by a Start
condition, generated by the bus master. The Start condition is followed by a Device Select
code and Read/Write bit (RW) (as described in
Inside this Device Select code, the 4-bit device type identifier code is (1010) for the M24C32
and (1011) for the M24C32-D.
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Logic diagram
Doc ID 4578 Rev 18
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table
4), terminated by an acknowledge bit.
th
bit