m95020-w STMicroelectronics, m95020-w Datasheet
m95020-w
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m95020-w Summary of contents
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... More than 40-year data retention Packages – ECOPACK® (RoHS compliant) Table 1. Product list Reference M95040 M95040 M95040-W M95040-R M95020 M95020 M95020-W M95020-R M95010 M95010 M95010-W M95010-R November 2006 Part Number Rev 7 M95040 M95020 M95010 with high speed Clock SO8 (MN) ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE 6.7 Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ...
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... Table 24. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 37 Table 25. UFDFPN8 (MLP8) - 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 26. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4/42 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Hold Condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 ...
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... Summary description The M95040 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken Low ...
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... M95040, M95020, M95010 Table 2. Signal names HOLD Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground Summary description 7/42 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 8/42 must be held stable and within the specified valid range: CC Table 13 to Table 17). These signals are described next. M95040, M95020, M95010 , IH ...
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... M95040, M95020, M95010 2.6 Write Protect (W) This input signal is used to control whether the memory is write protected. When Write Protect (W) is held Low, writes to the memory are disabled, but other operations remain enabled. Write Protect (W) must either be driven High or Low, but must not be left floating. ...
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... At Power-down, the device must be deselected and in Standby Power mode (that is there should be no internal Write cycle in progress). Chip Select (S) should be allowed to follow the voltage applied on V 10/ soon M95040, M95020, M95010 drops from the normal CC ...
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... M95040, M95020, M95010 3 Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low ...
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... Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 4. SPI modes supported CPOL CPHA 12/42 MSB M95040, M95020, M95010 Figure 4, is the clock polarity when the MSB AI01438B ...
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... M95040, M95020, M95010 4 Operating features 4.1 Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. ...
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... Array Addresses Protected Protected Block M95040 none none Upper quarter 180h - 1FFh Upper half 100h - 1FFh Whole memory 000h - 1FFh M95040, M95020, M95010 M95020 M95010 none none C0h - FFh 60h - 7Fh 80h - FFh 40h - 7Fh 00h - FFh 00h - 7Fh ...
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... M95040, M95020, M95010 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD W Control Logic Address Register and Counter Figure 6. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Memory organization Status Register Size of the Read only EEPROM area ...
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... Read from Memory Array Write to Memory Array 7, to send this instruction to the device, Chip Select (S) is driven Low Instruction D High Impedance Q M95040, M95020, M95010 Table 4. Table 4), the device automatically Instruction Format (1) 0000 X110 (1) 0000 X100 (1) 0000 X101 (1) 0000 X001 ...
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... M95040, M95020, M95010 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High ...
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... Hardware Protected mode has not been set. Table 5. Status Register format 18/ send this instruction to the device, Chip Select (S) is first driven Table 3) becomes protected against Write 1 1 BP1 M95040, M95020, M95010 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...
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... M95040, M95020, M95010 Figure 9. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI01444D 19/42 ...
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... Chip Select (S) is first driven (as specified in Table Instruction 7 6 High Impedance MSB M95040, M95020, M95010 Table 22), at the end of which the Write Status Register AI01445B ...
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... M95040, M95020, M95010 6.5 Read from Memory Array (READ) As shown in Figure Low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in register, and the byte of data at that address is shifted out, on Serial Data Output (Q) ...
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... Instruction Byte Address Table 6, the most significant address bits are Don’t Care. M95040, M95020, M95010 12, this occurs after the eighth bit of the (as specified in WC Figure 13, the next byte Data Byte ...
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... M95040, M95020, M95010 Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown in 6.7 Cycling Instruction Byte Address ...
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... The BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0. 24/42 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability ...
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... Input and Output Timing Reference Voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 14. AC test measurement I/O waveform 26/42 Parameter Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC M95040, M95020, M95010 Min. Max. Unit 4.5 5.5 –40 85 °C –40 125 °C Min ...
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... M95040, M95020, M95010 Table 12. Capacitance Symbol C Output Capacitance (Q) OUT C Input Capacitance (D) IN Input Capacitance (other pins) 1. Sampled only, not 100% tested Table 13. DC characteristics (M950x0, Device Grade 6) Symbol Parameter I Input Leakage Current LI Output Leakage I LO Current I Supply Current CC Supply Current ...
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... Current I Supply Current CC Supply Current I CC1 (Standby Power mode) V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 28/42 M95040, M95020, M95010 Test Condition OUT 0.1V /0. MHz ...
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... M95040, M95020, M95010 Table 18. AC characteristics (M950x0, Device Grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock Low Setup Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time M95040, M95020, M95010 and Table 8 Min. Max. Unit D.C. 5 MHz ...
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... M95040, M95020, M95010 Table 20. AC characteristics (M950x0-W, Device Grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock Low Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time M95040, M95020, M95010 Table 11 and Table 9 Min. Max. D. ...
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... M95040, M95020, M95010 Table 22. AC characteristics (M950x0-R) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH ...
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... DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/42 tSLCH tCHDX tCLCH MSB IN High Impedance tHLCH tCLHL tHLQZ M95040, M95020, M95010 tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B ...
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... M95040, M95020, M95010 Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tQLQH tQHQL DC and AC parameters tCL tSHQZ LSB OUT AI01449e 35/42 ...
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... Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4.80 5.00 6.00 5.80 6.20 3.90 3.80 4.00 1.27 – – 0.25 0.50 0° 8° 0.40 1.27 1.04 M95040, M95020, M95010 h x 45˚ c 0.25 mm GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 Max 0.069 0.010 0.019 ...
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... M95040, M95020, M95010 Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Drawing is not to scale. Table 24. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data Symbol (number of pins ...
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... D D2 ddd (number of pins) 38/ ddd A1 millimeters Typ Min 0.55 0.50 0.00 0.25 0.20 2.00 1.55 3.00 0.15 0.50 – 0.45 0.40 0.30 8 M95040, M95020, M95010 UFDFPN-01 inches Max Typ Min 0.60 0.022 0.020 0.05 0.000 0.30 0.010 0.008 0.079 1.65 0.061 0.05 0.118 0.25 0.006 – 0.020 – 0.50 0.018 0.016 0.15 0.012 8 Max ...
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... M95040, M95020, M95010 11 Part numbering Table 26. Ordering information scheme Example: Device Type M95 = SPI serial access EEPROM Device Function 040 = 4 Kbit (512 x 8) 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating Voltage blank = V = 4 2 1.8 to 5.5V CC Package MN = SO8 (150 mil width TSSOP8 (169 mil width UFDFPN8 (MLP8) 2 × ...
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... Absolute Maximum Ratings for V Soldering temperature information clarified for RoHS compliant devices. 5.0 New 5V and 2.5V devices, with process letter W, promoted from preliminary data to full data. Device Grade 3 clarified, with reference to HRCF and automotive environments M95040, M95020, M95010 Changes , t substituted in AC CHHL CHHH (min) improved to -0 ...
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... M95040, M95020, M95010 Table 27. Document revision history (continued) Date Version 05-Oct-2004 06-Nov-2006 Product List summary table added. Process identification letter “G” information added. Order information for Tape and Reel changed to T. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX 6.0 corrected to tHHQV. Signal Description updated. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M95040, M95020, M95010 ...