lh28f400su-nc Sharp Microelectronics of the Americas, lh28f400su-nc Datasheet - Page 4

• Manufacturer Part Number: lh28f400su-nc
• Description: 512k 256k Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F400SU-NC
PIN DESCRIPTION
4
DQ
DQ
DQ
SYMBOL
A
A
RY
13
BYTE
0
8
GND
0
15
V
V
WE
CE
RP
OE
NC
- A
- DQ
- A
- DQ
PP
CC
»
/ BY
- A
»
»
»
12
17
-1
»
15
7
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
TYPE
BYTE-SELECT ADDRESSES: Selects between high and low byte when device is in
x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
DQ
WORD-SELECT ADDRESSES: Select a word within one 16K block. These
addresses are latched during Data Writes.
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS: Inputs data during x16 Data Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
DQ
CHIP ENABLE INPUT: Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE
RESET/POWER-DOWN: With RP
aborted and device is put into the deep power down mode. When the power is
turned on, RP
figuration. When the power transition is occurred, or the power on/off, RP
required to stay low in order to protect data from noise. When returning from Deep
Power-Down, a recovery time of 430 ns is required to allow these circuits to power
up. When RP
and the device is reset. All Status registers return to ready (with all status flags
cleared). After returning, the device is in read array mode.
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation or
Erase is Suspended, or the device is in deep power-down mode RY
BYTE ENABLE : BYTE low places device in x8 mode. All data is then input or
output on DQ
and low byte. BYTE high places the device in x16 mode, and turns off the A
input buffer. Address A
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks
or writing words/bytes into the flash array.
DEVICE POWER SUPPLY (3.3 V ±0.3 V): Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NO CONNECT: No internal connection to die, lead may be driven or left floating.
15
15
/A
/A
-1
-1
input buffer is turned off when BYTE is high).
is address.
0
»
»
goes low, any current or pending WSM operation(s) are terminated,
pin is turned to low in order to return the device to default con-
- DQ
7
, and DQ
0
, then becomes the lowest order address.
»
must be low to select the device.
8
NAME AND FUNCTION
- DQ
»
low, the device is reset, any current operation is
»
15
is high.
float. Address A
4M (512K × 8, 256K × 16) Flash Memory
-1
selects between the high
»
/ BY
»
pin is floated.
»
is
-1