at45db321c ATMEL Corporation, at45db321c Datasheet - Page 23

• Manufacturer Part Number: at45db321c
• Description: 32-megabit 2.7 Volt Dataflash At45db321c For New Designs Use At45db321d
• Manufacturer: ATMEL Corporation

11. Input Test Waveforms and Measurement Levels
12. Output Test Load
13. AC Waveforms
13.1
3387M–DFLASH–2/08
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
SCK
SO
CS
SI
t
Four different timing waveforms are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK
signal is still low (SCK low time is specified as t
idS serial interface but for frequencies up to 33 MHz and are compatible with SPI Mode 0 and
SPI Mode 3 respectively. Waveforms 1 and 2 are also compatible with inactive clock polarity low
and inactive clock polarity high, since the maximum specified frequency in that case is 33 MHz.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the t
imum frequency = 40 MHz) of the RapidS serial case.
R
HIGH IMPEDANCE
, t
F
DRIVING
< 2 ns (10% to 90%)
LEVELS
AC
t
SU
t
CSS
VALID IN
WL
3.0V
0V
period. These timing waveforms are valid over the full frequency range (max-
t
WH
DEVICE
UNDER
t
V
TEST
t
H
t
WL
VALID OUT
1.5V
t
HO
30 pF
AC
MEASUREMENT
LEVEL
t
CSH
WL
). Timing waveforms 1 and 2 conform to Rap-
HIGH IMPEDANCE
t
t
DIS
CS
AT45DB321C
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