is24c32c-2pli-tr Integrated Silicon Solution, Inc., is24c32c-2pli-tr Datasheet

no-image

is24c32c-2pli-tr

Manufacturer Part Number
is24c32c-2pli-tr
Description
32k-bit 2-wire Serial Cmos Eeprom
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
IS24C128B
IS24C128B
2-WIRE (I
C)
2
128K-bit
SERIAL EEPROM
Intregrated Silicon Solution, Inc. - www.issi.com
1
Rev. 00F
09/18/09

Related parts for is24c32c-2pli-tr

is24c32c-2pli-tr Summary of contents

Page 1

IS24C128B 2-WIRE (I SERIAL EEPROM Intregrated Silicon Solution, Inc. - www.issi.com Rev. 00F 09/18/09 IS24C128B 128K-bit ...

Page 2

... Ordering Information ……………………………………………………..............15 Packaging Information ….………………………………………………..............16 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 ...

Page 3

... Packages: SOIC/SOP (JEDEC) and TSSOP Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip- ment, aerospace systems, or for other applications planned to support or sustain life ...

Page 4

... IS24C128B FUNCTIONAL BLOCK DIAGRAM Vcc SDA SCL WP SLAVE ADDRESS REGISTER & COMPARATOR GND nMOS 4 CONTROL LOGIC WORD ADDRESS COUNTER ACK Clock DI/O Integrated Silicon Solution, Inc. — www.issi.com HIGH VOLTAGE GENERATOR, TIMING & CONTROL EEPROM ARRAY Y DECODER > DATA REGISTER Rev. 00F 09/18/09 ...

Page 5

... The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire Or'ed with other open drain or open collector outputs. The SDA bus a pullup resistor to Vcc. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 VCC WP ...

Page 6

... Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 ...

Page 7

... Slave Device Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data word stored at address location n+1. The Master should not acknowledge the transfer but should Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 generate a Stop condition so the IS24C128B discontinues transmission ...

Page 8

... Figure 1. Typical System Bus Configuration SDA SCL Figure 2. Output Acknowledge SCL from Master Data Output from Transmitter Data Output from Receiver Figure 3. Start and Stop Conditions SCL SDA 8 Vcc Master IS24C128B Transmitter/ Receiver Integrated Silicon Solution, Inc. — www.issi.com ACK Rev. 00F 09/18/09 ...

Page 9

... Device R T Word Address (n) Address T E SDA A Bus Activity R/W Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 Data Change Data Stable Data Stable Word Address Word Address ...

Page 10

... R/W Word Word Address (n) Address ( Data Byte n Data Byte n Integrated Silicon Solution, Inc. — www.issi.com Device A R Address Data Don't care bit Data Byte n+2 ...

Page 11

... The slave does not provide an acknowledgement if the Deep Sleep Mode is enabled, and after stop, it begins to exit. Figure 12 DEEP SLEEP VERIFICATIOn * The slave does not provide an acknowledgement if the Deep Sleep Mode is already enabled. This command does not affect Deep Sleep. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 W ...

Page 12

... max Test Conditions Read at 400 KHz (Vcc = 1.8V) Write at 400 KHz (Vcc = 1.8V) Vcc = 1.8V Vcc = 2.5V Vcc = 5.0V Conditions Max ouT Integrated Silicon Solution, Inc. — www.issi.com V V °C °C mA Min. Max. — 0.2 — 0 –0 — 3 — ...

Page 13

... SCL and SDA Rise Time ( SCL and SDA Fall Time ( Write Cycle Time WR notes: 1. This parameter is characterized but not 100% tested. 2. The timing is referenced to half Vcc level. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 1.8V ≤ Vcc < 2.5V Min. Max. 0 400 — 50 1.2 — 0.6 — ...

Page 14

... SCL t SU:STA SDA IN SDA OUT WP Figure 14. Write Cycle Timing SCL SDA 8th BIT WORD HIGH LOW t HD:DAT t t HD:STA SU:DAT ACK t WR STOP Condition Integrated Silicon Solution, Inc. — www.issi.com t SU:STO t BUF t SU:WP t HD:WP START Condition Rev. 00F 09/18/09 ...

Page 15

... For tube/bulk packaging, if available, remove “-TR” at the end of the P/N. 4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable. 5. ISSI offers Industrial grade for Commercial applications (0 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 Package Type* (8-pin) 150-mil SOIC (JEDEC ...

Page 16

... IS24C128B 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 ...

Page 17

... IS24C128B Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 17 ...

Related keywords