is45s16400e Integrated Silicon Solution, Inc., is45s16400e Datasheet - Page 34

• Manufacturer Part Number: is45s16400e
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
IS45S16400E
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
34
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing CAS latency later.
The PRECHARGE to bank n will begin after t
where t
The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
Internal States
COMMAND
Internal States
ADDRESS
COMMAND
ADDRESS
BANK m
WR
BANK n
BANK m
BANK n
begins when the READ to bank m is registered.
CLK
DQ
CLK
DQ
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
BANK n,
WRITE - AP
T1
BANK n
COL a
BANK n,
D
Page Active
BANK n
T1
COL a
D
IN
WRITE with Burst of 4
IN
a
a
Page Active
WRITE with Burst of 4
D
T2
NOP
D
T2
IN
NOP
IN
a+1
WR
a+1
is met,
READ - AP
BANK m,
BANK m
T3
COL b
T3
D
NOP
Interrupt Burst, Write-Back
IN
a+2
t
CAS Latency - 3 (BANK m)
WR
4. Interrupted by a WRITE (with or without auto precharge):
- BANK n
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
WR
T4
WRITE - AP
NOP
BANK m,
BANK m
T4
Integrated Silicon Solution, Inc. — www.issi.com
COL b
D
READ with Burst of 4
Interrupt Burst, Write-Back
is met, where t
IN
b
t
WR
WRITE with Burst of 4
- BANK n
T5
NOP
T5
D
NOP
IN
b+1
WR
begins when the WRITE to bank
T6
NOP
T6
D
D
NOP
Precharge
IN
t
OUT
RP - BANK n
b+2
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
NOP
D
T7
D
NOP
Precharge
OUT
Write-Back
IN
t
RP - BANK m
b+3
t
b+1
RP - BANK m
02/04/08
Rev. A