74LVTH162374MEA Fairchild Semiconductor, 74LVTH162374MEA Datasheet
74LVTH162374MEA
Specifications of 74LVTH162374MEA
Related parts for 74LVTH162374MEA
74LVTH162374MEA Summary of contents
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... Charged-device model > 1000V Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Information Package Order Number Number (1) 74LVTH162374GX BGA54A (Preliminary) 74LVTH162374MEA MS48A 74LVTH162374MEX MS48A 74LVTH162374MTD MTD48 74LVTH162374MTX MTD48 Notes: 1. BGA package available in Tape and Reel only. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev ...
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... Pin Assignments for SSOP and TSSOP Pin Assignment for FPGA (Top Thru View) Pin Description Pin Name Description OE Output Enable Input (Active LOW Clock Pulse Input n I –I Inputs –O 3-STATE Outputs Connect ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 FBGA Pin Assignments ...
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... Logic Diagrams Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 flip-flop will store the state of their indi-vidual D-type inputs that meet the setup and hold time requirements ...
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... Input Voltage I I HIGH Level Output Current OH I LOW Level Output Current OL T Free-Air Operating Temperature Input Edge Rate, V ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 Conditions Output in 3-STATE Output in HIGH or LOW State V < GND I V < GND O V > V Output at HIGH State ...
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... An external driver must source at least the specified current to switch from LOW-to-HIGH external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than V ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 V ...
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... The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL (9) Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD Note: 9. Capcitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 (6) Conditions 50pF ( 500 L 3.3 OL 3.3 ...
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... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 Package Number BGA54A (Preliminary) 7 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 Package Number MS48A 8 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide ©2000 Fairchild Semiconductor Corporation 74LVTH162374 Rev. 1.0.0 Package Number MDT48 9 www.fairchildsemi.com ...
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... TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ® ...