nsbmc290 National Semiconductor Corporation, nsbmc290 Datasheet - Page 8

• Manufacturer Part Number: nsbmc290
• Description: Burst Mode Memory Controller
• Manufacturer: National Semiconductor Corporation

Functional Description
Note 1 Remains active over the entire burst cycle regardless of the bank being accessed
Note 2 Asserted only when the specific bank is being accessed
Note 3 Must be externally synchronized to SYSCLK
The memory buffer strategy required will depend on the
type of DRAMs being used (bit wide vs nibble wide compo-
nents) the access time of these memories the desired
burst write speed and the system clock speed Table III
presents some of the possible configurations with the corre-
sponding mode settings For a comprehensive discussion of
the selection of a buffer strategy lease refer to the
NSBMC290 Application Guide This document expands the
rationale of the selection process and presents specific ap-
plication examples and circuit diagrams
SYSTEM CLOCK FREQUENCY
The system clock frequency is used to derive the period of
DRAM refresh cycles The refresh rate is given by (system
clock frequency) (16 x (programmed value
the nominal refresh requirements for DRAM devices For
74F245
74F245
74F245 74F646
74F245 74F646
Am29C983
29827 29861
Buffer Type
DBTX
DBTXa
DBTXb
DBCE
DBCEa
DBCEb
IBTX
IBTXa
IBTXb
BankB A (Note 3)
Signal Name
Memory Buffer Configurations
TABLE III Possible NSBMC290
Organization
TABLE II Buffer Control Signals and the Memory Bank for Which they are active
DRAM
Nibble
Nibble
Bit
Bit
Bit
Bit
2 Cycle
2 Cycle
1 Cycle
1 Cycle
1 Cycle
2 Cycle
Burst
Write
(Continued)
Read
A B
A B
A B
A
B
A
B
A
B
Simple Pipeline Cycle
a
1)) This meets
Buffer Mode
Mode 3
Mode 1
Mode 3
Mode 1
Mode 2
Mode 0
BMC
1
e
Memory Bank B is next active 0
8
Write
A B
A
B
example if the system clock is 25 MHz and the pro-
grammed value is 24 the NSBMC20 will execute the 256
refresh cycles for a 256k DRAM in 4 096 ms Bit 13 of the
configuration word in the MSB of the frequency field while
bit 8 is the LSB The refresh algorithm employed by the
NSBMC290 guarantees the time for complete device re-
fresh however the time for individual row refreshes may be
held off to prevent the preemption of a burst
DRAM SIZE
This two bit field bit 7 and bit 6 configures the NSBMC290
for the correct memory address size and hence total mem-
ory block size Note that the memory in both banks of the
block are required to be of the same size and organization
in order for correct operation to occur Table IV lists the
supported device sizes
(in Bits 7 6)
Size Code
Memory
0
1
2
3
TABLE IV Size Code Settings DRAM
Density and Address Range Size
A B (Note 1)
A B (Note 1)
A B (Note 1)
A (Note 2)
B (Note 2)
A (Note 2)
B (Note 2)
A (Note 2)
B (Note 2)
256 kB x 1 256 kB x 4
64 kB x 1 64 kB x 4
1 MB x 1 1 MB x 4
4 MB x 1 4 MB x 4
Read
e
Address Size
Bank A is next
DRAM
Burst Cycle
A B (Note 1)
A B (Note 1)
A B (Note 1)
512 KBytes
Block Size
32 MBytes
Write
2 MBytes
8 MBytes
Memory