ncp1230a ON Semiconductor, ncp1230a Datasheet - Page 14

• Manufacturer Part Number: ncp1230a
• Description: Low?standby Power Soft Skip Mode Controller
• Manufacturer: ON Semiconductor

where:
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 33 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 125 msec timer starts, and if the
conditions is still present after the time output period, the
NCP1230A confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230A is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp−p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230A exits the skip mode, and returns
to normal operation.
FB
Eff = the power supply efficiency
During the soft skip mode the PFC_Vcc signal (pin 1) is
In Phase four, the output power demands have increases
Vdd
Vskip
+
+
1.25 V
0.75 V
Vskip
/ Vstby−out
R out + E out
Figure 32.
+
−
−
+
CS Cmp
P out
S is rising edge triggered
R is falling edge triggered
2
S
125 ms
R
PFC_V
Latch
Reset
CC
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14
Leaving standby (Soft Skip Mode)
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 33.
Current Sense
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
maximum.
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 34).
Ramp Compensation
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
is summed internally through a 18 kW resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
NCP1230A, at 65 kHz the dv/dt of the ramp is 130 mV/ms.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 mH, and the SMPS has
Max I
1.25 V
0.75 V
When the feedback voltage rises above the 1.25 volts
The NCP1230A is a peak current mode controller, where
There is a 18k resistor connected to the CS pin, the other
In Switch Mode Power Supplies operating in Continuous
The NCP1230A provides an internal 2.3 Vpp ramp which
If we assume we are using the 65 kHz version of the
P
PFC is Off
Regulation
PFC is On
Figure 33.
Skip + 60%
PFC is Off
125 ms
Delay
No Delay
PFC is On