ncp1239f ON Semiconductor, ncp1239f Datasheet
ncp1239f
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ncp1239f Summary of contents
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... Offline Battery Chargers • Telecom and PC Power Supplies • Flyback Applications (NCP1239F) and Forward Applications (NCP1239V) *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 October, 2005 − ...
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... Vbulk Rbo1 to PFC_V CC OVP REF5V NTC REF5V (5V/10mA) Thermistor + Cbulk BO Rbo2 Rt Cbo Css Figure 1. NCP1239F Typical Application Example Vbulk Rbo1 to PFC_V CC OVP REF5V NTC REF5V (5V/10mA) Thermistor + Cbulk BO Rbo2 Rt Cbo Css Figure 2. NCP1239V Typical Application Example NCP1239 ...
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... T = 25°C, for min/max values T J Rating Going mA) Rt NCP1239F NCP1239V NCP1239F (65 kHz) NCP1239V (118 kHz) NCP1239F (100 kHz) NCP1239V (182 kHz) NCP1239F (130 kHz) NCP1239V (236 kHz Pin http://onsemi.com 3 Symbol Value V ...
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... Recommended Switching Frequency Range Vosc Pin 4 Voltage @ Rt = 100 kW Kosc Product (Switching Frequency times the Rt Pin 4 resistance) (Note kHz and 130 kHz (NCP1239F) @ 118 kHz and 236 kHz (NCP1239V) Dfsw Internal Modulation Swing, in percentage of fsw Dmax Maximum Duty−Cycle Current Limitation I Maximum Internal Set− ...
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... Thermal Shutdown Threshold Hysteresis Vfault Fault Detection Threshold ORDERING INFORMATION Device NCP1239FDR2 NCP1239FDR2G NCP1239VDR2 NCP1239VDR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NCP1239 (For typical values T = 25° ...
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... Pin 4 resistor allows a precise frequency programming. The circuit is optimized to operate between 50 kHz and 150 kHz (NCP1239F) and between 100 kHz and 250 kHz (NCP1239V). This pin receives a portion of the bulk capacitor to authorize operation above a certain level of mains only ...
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... Compensation BO_in BO 5 − 0.5V / 0.25V Vdd Oscillator 4 − 2.5V “Jittered” Reference Vdd 20k Skip Figure 3. NCP1239F Internal Circuit Architecture NCP1239 Skip Stby_detect Internal Thermal Shutdown TSD OVL S regOUT Fault Vdd Vcc < 4V stdwn Stby Startup Phase ...
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FB<Vpin1 => Skip high + − FB 100k Skip 7 adjust + 15r 450mV + 25r − FB>1.6*Vpin1 =>Stby_detect RESET Fault 3 − detect + 2.5V Vcc 10k PFC_Vcc 1 pfcON pfcOFF 1mA Stby Vdd Vdd timer ...
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TYPICAL PERFORMANCE CHARACTERISTICS 6.0 5.0 4.0 3.0 2.0 1.0 0 − TEMPERATURE (°C) Figure 5. High Voltage Current Source vs. Temperature @ V CC 6.0 5.0 4.0 3.0 2.0 1.0 0 − ...
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... TEMPERATURE (°C) Figure 11. V Latched−Off vs. Temperature CC 5.0 130 kHz 4.5 100 kHz 4.0 3.5 65 kHz 3.0 2.5 2.0 − TEMPERATURE (°C) Figure 13. NCP1239F Circuit Consumption ( driver Pin 12) vs. Temperature 0.6 0.5 0.4 0.3 0.2 0.1 0 − TEMPERATURE (°C) Figure 15. Latched−Off Mode Consumption vs. Temperature NCP1239 2.8 2.6 2.4 2.2 2.0 1.8 1.6 75 100 125 − ...
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... TEMPERATURE (°C) Figure 19. Driver Voltage Clamp vs. Temperature 6700 6650 6600 6550 6500 6450 6400 − TEMPERATURE (°C) Figure 21. Oscillator K Parameter vs. Temperature osc (K = fsw * R ) (NCP1239F) osc pin4 NCP1239 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1 100 125 − 100 125 − ...
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... TYPICAL PERFORMANCE CHARACTERISTICS 180 160 140 120 100 − TEMPERATURE (°C) Figure 23. Pin 9 Current vs. Temperature (@ V = 0.5 V) (NCP1239F) pin9 0.920 0.915 0.910 0.905 0.900 0.895 0.890 0.890 0.885 0.880 − TEMPERATURE (°C) Figure 25. Maximum Current Setpoint vs. ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.245 0.244 0.243 0.242 0.241 0.240 0.239 0.238 0.237 0.236 0.235 − TEMPERATURE (°C) Figure 29. Brown−Out Low Threshold vs. Temperature 24.5 24.3 24.1 23.9 23.7 23 TEMPERATURE (°C) Figure ...
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Fault not confirmed 100ms* 4.3V 3.0V 1.8V fmax fmin 0.9 V Error flag PFC off DRV Vcc 16.4V 11.2V 6. *This time is programmed by the Pin 6 capacitor. C − Soft−Start Time (T ss − Jittering ...
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Vpin6 4.3V (SS/timer) 3.0V 1.8V 100ms* PFC running Drv FB FB−skip (Vpin7 Stby_detect latch is armed Stby_detect latch is reset *This time is programmed by the Pin 6 capacitor. C − Soft−Start Time (T ):7 ...
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... Subharmonic oscillations can thus be fought via the inclusion of a simple resistor, 500 mV Current Sense threshold for Over Power Limit (NCP1239F): the NCP1239 operating in current mode, the circuit Pin 10 monitors the current to modulate its level according to the power demand. Due to the ramp compensation, one must generally note that the Pin 10 voltage is not the exact image of the inductor current ...
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... Pin 10 monitors the power switch current and compares it to the current setpoint (one third of the feedback voltage). The current setpoint is limited by the soft−start during the power−on sequence and permanently clamped to 0 the NCP1239F, a second pin (Pin 9) monitors the current to clamp the power. NCP1239 ...
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Figure 37 depicts the V evolution during a proper startup sequence, showing the state of the error flag: CC Vcc VccON VccOFF FB Full power User Powers up! Ip max Error 7.5ms* Flag SS Timer *This time is programmed by ...
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PFC Startup Sequence To ensure an adequate startup sequence of both PWM section and the PFC stage, some logic and timing need to be included as shown on the internal diagram. The key point here is the fact that the ...
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Vcc PWM Stby stby is left 16.4V 11.2V 6.9V Timer 100ms* 100ms* 0.9V flag 7.5ms* SS PFC Vcc Standby is confirmed *This time is programmed by the Pin 6 capacitor. C − Soft−Start Time (T ):7 − ...
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The PFC controller connection is really straightforward as testified by Figure 39: simply connect to Pin 1, the base of a pnp transistor that connects the PFC’s V one (perhaps add a small decoupling capacitor like a 0 ...
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The leakage effect seen on the auxiliary side pulls−up the final level peak−rectified by the diode On Figure 40’s example, one can clearly observe the difference between the peak and the real ...
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V CC Drv 100ms Bunch length given by timer When V drops faster than the timer, it prematurely interrupts the pulses flow. CC The 100 ms delay could be shortened or lengthened by changing the Pin 6 capacitor ...
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If by design we have selected becomes easy to evaluate the burst period and its duty−cycle. This can be done by properly identifying all time events on Figure 42 and applying the classical formula ...
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Pin 3 can serve to build an Overvoltage Protection by placing a Zener between the voltage to measure (e.g., V and Pin 3 (refer to application schematic Zener is applied, the Pin 3 comparator will switch ...
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Figure 45 offers a way to connect the elements around Pin 5 to create a Brown−Out detection: AC line Example where the voltage of the bulk capacitor is used for the brown−out Protection The calculation procedure for Rupper and Rlower ...
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B1 V(line)*V(timing) Vline Voltage bulk line timing Rupper 2.4Meg V1 V2 Rlower 10k V2 timing 0 PWL 0 0 10s 0.2 V1 line 0 SIN 0 150 50 A simple simulation configuration helps to tailor the ...
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... Cfil = 1 mF, One obtains the following voltage thresholds: − Vtrip = 85 Vrms, − VBO = 65 Vrms. Over Power Limit (NCP1239F) Overload conditions may push the converter to draw an excessive power (which generally increases versus the input voltage). One must avoid such a behavior: a) not to have to dimension the converter for a power ...
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DI HL High Input Voltage The propagation delay (Dt) produces overcurrents (DI voltage consequence, the actual maximum current and then the power limit gets higher when the AC line increases. Vocp ) Vin @ dt I max + ...
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... Please Dmax note that Cosc and Iosc are the internal capacitor and current (respectively), that set the switching period (T). Hence, Cosc is a constant and K Iosc @ T switching frequency. In the NCP1239F, the maximum duty−cycle is fixed (80% typically). http://onsemi.com 30 Vin Rbo1 Rbo2 Cbo ...
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Soft−Start The NCP1239 features an internal soft−start activated during the Power On sequence (PON). As soon as V reaches 16.4 V, the current setpoint is gradually increased from nearly zero up to the maximum clamping level (e.g. 0.9 V/Rsense). This ...
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In the NCP1239, the ramp features a swing of 3.2 V. Suppose we select a 65 kHz version. Over a 65 kHz frequency, it corresponds to a 130 mV/ms ramp. In our FLYBACK design, let’s assume that our primary inductance ...
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Skipping Cycle Mode The NCP1239 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, Pin 8 imposes a current setpoint accordingly to the load ...
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The skip−cycle takes place at low peak currents which guaranties noise free operation PFC Inhibition in Standby The circuit detects a light load condition by permanently monitoring the skip−cycle comparator activity: in normal load condition ...
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One clearly sees that the GTS signal does not react to the fugitive low FB Pin condition during startup REF5V Skip R1 Adjust 100k 7 R2 Suppose our Flyback controller is built with a transformer primary inductance of 250 mH. ...
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The following plots were obtained using a 150 W application (output 19 V/7 A). The NCP1239 enables the PFC V as soon as the FB pin voltage has gone below a threshold (about 2.7 V), that is when the CC ...
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When the load current falls to a low level (CH4), the FB pin voltage diminishes to take into account the decay of the power demand consequence, the FB pin voltage goes below the “Vskip” threshold and the soft ...
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... American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 38 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...