lt3692a Linear Technology Corporation, lt3692a Datasheet

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lt3692a

Manufacturer Part Number
lt3692a
Description
Monolithic Dual Tracking 3.5a Step-down Switching Regulator
Manufacturer
Linear Technology Corporation
Datasheet

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FEATURES
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APPLICATIONS
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L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
TYPICAL APPLICATION
550KHz
V
PG
OUT1
Wide Input Range:
– Operation from 3V to 36V
– OVLO Protects Circuit Through 60V Transients
Independent Supply, Shutdown, Soft-Start, UVLO,
Programmable Current Limit and Programmable
Power Good for Each 3.5A Regulator
Die Temperature Monitor
Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2.25MHz with
Synchronized Clock Output
Independent Synchronized Switching Frequencies
Optimize Component Size
Antiphase Switching
Outputs Can Be Paralleled
Flexible Output Voltage Tracking
Low Dropout: 95% Maximum Duty Cycle
5mm × 5mm QFN Package
FMEA Compliant 38-Pin Exposed Pad TSSOP Package
Automotive Supplies
Distributed Supply Regulation
3.3V
2.5A
0.1μF
3.3V and 1.2V 2-Stage Dual Step-Down Multi-Frequency Converter
100k
5.5V TO 36V
100k
33pF
V
IN1
0.22μF
47μF
8.06k
680pF
13k
4.7μF
68.1k
24.9k
4.7μH
100k
SHDN1
BST1
SW1
IND1
V
FB1
CMPI1
CMPO1
SS1
ILIM1
V
RT/SYNC
DIV
OUT1
C1
V
IN1
LT3692A
GND
CLKOUT
V
CMPO2
V
SHDN2
OUT1
CMPI2
V
IN2
ILIM2
BST2
IND2
SW2
OUT2
SS2
FB2
V
3.5A Step-Down Switching Regulator
C2
T
J
FB1
CLKOUT
2.2MHz
0.5μH
10nF
4.02k
40.2k
220pF
8.06k
0.1μF
100p
22pF
47μF
DESCRIPTION
The LT
DC/DC converter with two internal 3.8A switches. Independent
input voltage, shutdown, feedback, soft-start, UVLO current
limit and comparator pins for each channel simplify complex
power supply tracking and sequencing requirements.
To optimize efficiency and component size, both convert-
ers have a programmable maximum current limit and are
synchronized to either a common external clock input,
or a resistor settable fixed 250kHz to 2.25MHz internal
oscillator. A frequency divider is provided for channel 1
to further optimize component size. At all frequencies, a
180° phase relationship between channels is maintained,
reducing voltage ripple and component size. A clock output
is available for synchronizing multiple regulators.
Minimum input to output voltage ratios are improved by
allowing the switch to stay on through multiple clock cycles
only switching off when the boost capacitor needs recharg-
ing. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent current to <10μA.
The LT3692A is an improved version of the LT3692 with
reduced minimum on-time.
3692a TA01a
33.2k
V
1.2V
1A
2.2MHz
OUT2
Monolithic Dual Tracking
0.1μF
®
3692A is a dual current mode PWM step-down
Independent Synchronized Switching Frequencies
Extend Full Frequency Input Range
V
IN
= 30V
LT3692A
3692A TA01b
3692a TA01c
CH1:
550KHz
CH2:
2.2MHz
3692af
1

Related parts for lt3692a

lt3692a Summary of contents

Page 1

... Independent channel operation can be programmed using the SHDN pin. Disabling both converters reduces the total quiescent current to <10μA. The LT3692A is an improved version of the LT3692 with reduced minimum on-time. V OUT1 V ...

Page 2

... For more information on tape and reel specifications, go to: 2 RT/SYNC .....................................................................5V DIV, ILIM1/2 .............................................................3. .............................................................. ±100μA C1/2 J Operating Junction Temperature Range (Note 3) LT3692AEUH ..................................... –40°C to 125°C IN1/2 LT3692AIUH ...................................... –40°C to 125°C LT3692AEFE ...................................... –40°C to 125°C LT3692AIFE ....................................... –40°C to 125°C Storage Temperature Range .................. –65°C to 150°C 24 ILIM1 23 V ...

Page 3

... CMPO1/2 V Rising CMPI1/2 V Rising (Note 8) CMPI1/2 V CMPI1 0.6V 0.2V, CMPI1/2 CMPO1 0.36V RT/SYNC R =0Ω RT/SYNC R = 28k RT/SYNC R =100k RT/SYNC DIV RT/SYNC LT3692A MIN TYP MAX l 1.24 1.32 1.4 – 2.5 2.8 3 400 630 1000 l 790 806 822 ...

Page 4

... The LT3692AIUH/LT3692AIFE is guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125° ...

Page 5

... TEMPERATURE (°C) 750 740 730 720 710 700 690 680 670 660 650 50 75 100 125 150 3692a G07 LT3692A Shutdown Quiescent Current vs Temperature 125 150 75 –50 – TEMPERATURE (° ...

Page 6

... LT3692A TYPICAL PERFORMANCE CHARACTERISTICS Comparator Sink Current vs Temperature 400 SINK CURRENT 0.4V CMPO 350 300 250 200 150 100 50 0 –50 – 100 125 150 TEMPERATURE (°C) 3692a G09 CLKOUT-to-SW1 Delay vs Temperature 160 150 140 130 120 110 ...

Page 7

... CH2 = 3.5 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 85 3.0 80 2.5 75 2.0 70 1.5 1 12V 1MHz 60 0.5 SW CH1 = 2.5V CH2 = 2.5 3.0 3.5 4 3692a G23 LT3692A Minimum Boost Voltage vs Temperature 3. 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1. –50 – 100 TEMPERATURE (°C) 3692a G18 3.3V Efficiency and Power Loss 3.0 90 2.5 85 EFFICIENCY 2.0 80 1.5 75 POWER LOSS 1 ...

Page 8

... LT3692A PIN FUNCTIONS BST1/BST2: The BST pin provides a higher than V drive to the power NPN to ensure a low switch drop. If the voltage between the BST pin and the V the voltage required to fully turn on the power NPN, the power switch is turned off to recharge the BST capacitor. ...

Page 9

... When the current in the resistor exceeds the current dictated by the V pin, the SW latch is held in reset disabling C the output switch. Bias current flows out of the V IN LT3692A above the maximum switch C pin is also connected IN1 voltage must be greater than typically pin is also the collector ...

Page 10

... If the SHDN1 pin is taken below its 1.32V threshold the LT3692A will be placed in a low quiescent current mode. In this mode the LT3692A typically draws 6μA from V <1μA from V . When the SHDN pin is driven above 1.32V, the ...

Page 11

... CMPO output is an open-collector NPN that is off when the CMPI pin is above the threshold allowing a resistor to pull the CMPO pin to a desired voltage. The voltage present at the T temperature of the LT3692A. The T die temperature of 25°C and will have a slope of 10mV/°C. LT3692A voltage, output regulation is achieved by the pin voltage ...

Page 12

... R2 should be 10k or less to avoid bias current errors. Ref- erence designators refer to the Block Diagram in Figure 1. Choosing the Switching Frequency The LT3692A switching frequency is set by resistor R3 in Figure 1. The RT/SYNC pin is driven by a 12μA current source. Setting resistor R3 sets the voltage present at the RT/SYNC pin which determines the master oscillator frequency as illustrated in Figure 2 ...

Page 13

... The duty cycle is the fraction of time that the internal switch is on during a clock cycle. Unlike most fixed frequency regulators, the LT3692A will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. ...

Page 14

... V V – V IN(MAX MIN Note that the LT3692A will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the V and BST pins are not violated. IN However operation in this region of input voltage will exhibit pulse skipping behavior. ...

Page 15

... ILIM PIN RESISTOR (kΩ) Figure 6. Peak Switch Current vs ILIM Resistor Input Capacitor Selection Bypass the inputs of the LT3692A circuit with a 4.7μF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. When the LT3692A’ ...

Page 16

... IN With a shorted condition, diode current will increase to the typical value determined by the peak switch current limit of the LT3692A set by the ILIM pin. This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions can be tolerated. ...

Page 17

... For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3692A is turned on with its SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is ...

Page 18

... AGC loop will adjust slope compensation to avoid subharmonic oscillation. If the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10μs at which time the LT3692A reverts to the free-running frequency based on the RT/SYNC pin voltage. pin. Note that The synchronizing clock signal input to the LT3692A must ...

Page 19

... For CLK example, the input ripple voltage shown in Figure 12 for 3692a F09 a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V regulator is decreased from a peak of 472mV to 160mV as shown in Figure 13 by driving the LT3692A with a 71% duty cycle synchronization signal. INPUT RIPPLE V RT/SYNC t P Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° ...

Page 20

... When the input voltage drops back below 39V, the LT3692A goes through a POR cycle and the output soft-starts from its existing level to its regulation point. Additionally, an internal comparator will force both chan- ...

Page 21

... See the Typical Ap- plications circuit collection for examples. Output Tracking/Sequencing Complex output tracking and sequencing between channels can be implemented using the LT3692A’s SS and CMPO pins. Figure 14 shows several configurations for output tracking/sequencing for a 3.3V and 1.8V application. Independent soft-start for each channel is shown in Fig- ure  ...

Page 22

... R5 – + – V OUT2 R4 R6 FB2 CMPI2 R5 CMPO2 PG2 + – Figure 14. SS Pin Configurations Absolute Start-Up V OUT1 0.5V/DIV PG1 V OUT2 0.5V/DIV PG2 10ms/DIV LT3692A V OUT1 R1 R3 FB1 CMPI1 R2 2.5V CMPO1 PG1 12μA + 0.72V SS1 – 0.1μF V OUT2 R4 R6 FB2 CMPI2 R5 2.5V CMPO2 PG2 12μ ...

Page 23

... FB1 FB2 CMPI1 CMPI2 CMPO2 CMPO1 SS1 SS2 ILIM1 ILIM2 ILIM1 CLOCKOUT RT/SYNC CLKOUT 600kHz 820pF DIV T J GND 7.50k 15.8k 61.9k LT3692A 4.7μF 0.47μF V OUT2 3.3V 2A 47μF 24.9k 600kHz 8.06k 100k PG2 680pF 33pF 0.1μF 10nF 13.0k 3692a F15 3692af 23 ...

Page 24

... Figure 16. 3.3V and 1.2V 2-Stage Dual Step-Down Multi-Frequency Converter 24 4.7μ IN1 IN2 SHDN1 SHDN2 BST1 BST2 SW1 SW2 IND1 IND2 4.7μH 0.5μH LT3692A V V OUT1 OUT2 47μF 24.9k FB1 FB2 CMPI1 CMPI2 FB1 8.06k CMPO1 CMPO2 SS1 SS2 ILIM1 ILIM2 V ...

Page 25

... LT3692A is absent. This may occur in battery charging applications or in battery back-up systems where a battery or some other supply is diode OR-ed with the LT3692A’s output. If the V pin is allowed to float and the SHDN IN1/2 ...

Page 26

... Additionally, the SW and BST traces should be kept as short as possible. Thermal Considerations The PCB must also provide heat sinking to keep the LT3692A cool. The exposed metal on the bottom of the package must be soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias; ...

Page 27

... Inductor Resis tance R IND = Catch Diode Forward Voltage Drop Switch Boost Voltage V BOOST For the LT3692A demo board (see Figure 19) using the TSSOP package, the estimated junction temperature rise above ambient temperature is found by: ≈ 10 • (Power + Power T D1 RISETSSOP 12.3 • (Power ...

Page 28

... J Figure 21. Circuit to Generate the Negative Voltage Rail to Extend the safeguard, the LT3692A has an additional thermal shutdown threshold set at a typical value of 163°C for each channel. Each time the threshold is exceeded, a power on sequence for that channel will be initiated. The sequence will then repeat until the thermal overload is removed ...

Page 29

... SCOPE PROBE: 15pF SYNCHRONIZED LT3692A 500mV/DIV RT/SYNC PIN FET PROBE: 2pF 40ns/DIV FREQUENCY: 1.000MHz Figure 22. CLKOUT Rise Time SCOPE PROBE: 15pF CHARGE PUMP SYNCHRONIZED LT3692A RT/SYNC PIN 500mV/DIV FET PROBE: 2pF 20ns/DIV FREQUENCY: 1.000MHz Figure 23. CLKOUT Fall Time 3692a F22 3692a F23 3692af 29 ...

Page 30

... LT3692A TYPICAL APPLICATIONS 30 3692af ...

Page 31

... FB1 FB2 CMPI1 CMPI2 8.06k CMPO1 CMPO2 SS1 SS2 ILIM1 ILIM2 CLOCKOUT RT/SYNC CLKOUT 1600kHz 470pF DIV T J GND 33pF 16.5k 47.5k 100k LT3692A 1μH 0.22μF V OUT2 1.8V 1A 47μF 100pF 1600kHz 100k 8.06k PG 0.1μF 330pF 33pF 10nF 36.5k 40.2k 3692a TA03 3692af 31 ...

Page 32

... V IN 12V 4.7μ IN1 IN2 SHDN1 SHDN2 BST1 BST2 SW1 SW2 2.2μH 2.2μH IND1 IND2 LT3692A V V OUT1 OUT2 100pF 16.9k 24.9k FB1 FB2 CMPI1 CMPI2 CMPO2 CMPO1 SS1 SS2 ILIM1 ILIM2 CLOCKOUT RT/SYNC CLKOUT ...

Page 33

... ILIM1 IND1 LT3692A ILIM2 V OUT1 SS1 V OUT2 SS2 BST2 V C1 SW2 3.3μ IND2 CLOCKOUT CLKOUT 1MHz FB1 RT/SYNC CMPI1 T FB2 J DIV CMPO1 GND 10nF 3692a TA05 28k LT3692A 0.22μF V OUT 3.3V 5A 47μF ×2 2MHz EFFECTIVE RIPPLE 0.22μF 24.9k 8.06k 100k PG 3692af 33 ...

Page 34

... Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter 0.1μF 64.9k 36.5k 33pF 34 V IN1 12V 4.7μF 47. IN1 IN2 13k SHDN1 SHDN2 BST1 CMPO1 CMPO2 SW1 SS1 IND1 LT3692A SS2 V OUT1 ILIM1 V OUT2 ILIM2 BST2 V C1 SW2 V C2 680pF IND2 CLOCKOUT CLKOUT 2MHz FB1 RT/SYNC CMPI1 DIV FB2 ...

Page 35

... FB1 FB2 CMPI1 CMPI2 FB1 8.06k CMPO1 CMPO2 SS1 SS2 ILIM1 ILIM2 ILIM1 CLOCKOUT RT/SYNC CLKOUT 2MHz 680pF DIV T J GND 33pF 10k 61.9k 61.9k LT3692A 0.22μF V OUT2 1.8V 1A 47μF 10k 100pF 2MHz 8.06k 33pF 0.1μF 330pF 10nF 39.2k 3692a TA07 3692af 35 ...

Page 36

... LT3692A TYPICAL APPLICATIONS 36 3692af ...

Page 37

... FB2 FB1 CMPI2 100k 100°C CMPO2 TEMP FLAG SS2 SS1 ILIM2 ILIM1 CLOCKOUT 600kHz CLKOUT T J 2.2μF 28k 73.2k 0.1μF R14 49.9k 0.1μF LT3692A V OUT1 IN2 PV DDR IN 3.3μH V OUT2 3.3V PGOOD SW 2A 100μF RUN LT3612 FB 270k MODE ITH RT TRACK/SS 60 ...

Page 38

... LT3692A PACKAGE DESCRIPTION 4.75 REF 6.60 ±0.10 4.50 REF SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.50 – 0.75 0.09 – 0.20 (.0035 – .0079) (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 38 FE Package 38-Lead Plastic TSSOP (4.4mm) ...

Page 39

... Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC R = 0.05 0.75 ± 0.05 TYP 0.00 – 0.05 3.50 REF (4-SIDES) 0.200 REF LT3692A BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP R = 0.115 OR 0.35 × 45° CHAMFER TYP 31 32 0.40 ± 0. 3.45 ± 0.10 3.45 ± 0.10 (UH32) QFN 0406 REV D 0.25 ± ...

Page 40

... FAX: (408) 434-0507 ● 4.7μF 100k V V IN1 IN2 SHDN2 SHDN1 SHDN2 BST1 BST2 SW1 SW2 6.8μH 5.6μH IND1 IND2 LT3692A V V OUT1 OUT2 4.22k 2.49k FB1 FB2 806Ω CMPI1 CMPI2 CMPO1 CMPO2 SS2 SS1 SS2 ILIM2 ILIM1 ILIM2 ...

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