lt3071 Linear Technology Corporation, lt3071 Datasheet
lt3071
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lt3071 Summary of contents
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... All other trademarks are the property of their respective owners. Patents pending. 50k PWRGD V OUT OUT 0.9V 5A 2.2µF* 4.7µF* 10µF* *X5R OR X7R CAPACITORS V MON MON FULL SCALE 1k 0.01µF 3071 TA01a LT3071 5A, Low Noise, with Analog Margining . The LT3071’s high bandwidth RMS Dropout Voltage 150 OUT(NOMINAL) 120 1.8V OUT V = 3.3V BIAS 0.8V ...
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... SENSE Input................................................. –0. VIOC, PWRGD, I Outputs . ...................... –0. MON REF/BYP Output . .......................................... –0. Output Short-Circuit Duration . ......................... Indefinite Operating Junction Temperature (Note 2) LT3071E/LT3071I . ............................. –40°C to 125°C LT3071MP ......................................... –55°C to 125°C Storage Temperature Range .................. –65°C to 150°C orDer inFormAtion LEAD FREE FINISH TAPE AND REEL LT3071EUFD#PBF LT3071EUFD#TRPBF ...
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... BIAS – 0.3V 0.8V, 1.8V IN OUT OUT ≤ 5A, V – 0.3V 0.8V, 1.8V OUT IN OUT OUT = 1.8V OUT , V Rising OUT(NOMINAL) OUT , V Falling OUT(NOMINAL) OUT = 200µA (Fault Condition) LT3071 = V + 0.3V (Note 5 2.5V unless IN OUT BIAS MIN TYP MAX 0.95 l 2.2 l 0.792 0.800 0.808 l 0.891 0.900 0.909 l 0.990 1.000 1.010 l 1 ...
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... P-P RIPPLE = 300mV 2.5A OUT OUT = 10nF , BW = 10Hz to 100kHz = 5A 10nF , C = 15µF , OUT REF/BYP OUT Note 5: The LT3071 incorporates safe operating area protection circuitry. Current limit decreases as the V foldback starts at V Characteristics for a graph of Current Limit vs V current limit foldback feature is independent of the thermal shutdown circuity. = 25°C. A Note 6: Dropout voltage, V differential at a specified output current. In dropout, the output voltage equals V – Note 7: GND pin current is tested with V current source load ...
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... BIAS VOLTAGE (V) Output Voltage (1.2V) vs Temperature 1.212 I = 10mA LOAD 1.208 1.204 1.200 1.196 1.192 1.188 –75 –50 – 100 125 175 TEMPERATURE (°C) LT3071 Dropout Voltage vs Temperature 100 OUT(NOMINAL 2.5A OUT 3. 1.8V, V OUT = 2. 0.8V OUT = 3. 1.2V, V OUT ...
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... LT3071 typicAl perFormAnce chArActeristics Output Voltage (1.8V) vs Temperature 1.818 I = 10mA LOAD 1.814 1.810 1.806 1.802 1.798 1.794 1.790 1.786 1.782 –75 –50 – 100 125 150 TEMPERATURE (°C) 3071 G10 BIAS Pin Current in Nap Mode 400 V = 2.5V BIAS 350 EN 300 ...
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... TEMPERATURE (°C) LT3071 Logic Input Threshold Voltages Logic Hi-Z to High State Transitions 3 3.3V BIAS LOGIC Hi-Z TO HIGH THRESHOLD IS RELATIVE TO V VOLTAGE BIAS 2.9 SEE APPLICATIONS INFORMATION FOR MORE DETAILS 2.8 INPUT RISING LOGIC Hi-Z TO HIGH 2 ...
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... LT3071 typicAl perFormAnce chArActeristics Current Limit vs V – OUT 3.3V BIAS T = 25° 1.8V OUT 1.2V OUT V = 0.8V OUT 0 1.00 1.25 0 0.25 0.50 0.75 1.50 1.75 IN-TO-OUT VOLTAGE DIFFERENTIAL (V) 3071 G26 IN Pin Ripple Rejection 117µF 30 OUT C = 16.9µF OUT OUT ...
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... OUTPUT CURRENT (A) Output Noise (10Hz to 100kHz) V OUT 100µV/DIV 1ms/DIV OUT OUT C = 16.9µF OUT 10 LT3071 Input Voltage Line Regulation 300 V = 3.3V BIAS V = 2.05V TO 2.7V IN 250 V = 1.8V OUT I = 10mA OUT 200 150 100 50 0 150 175 –75 – ...
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... LT3071 typicAl perFormAnce chArActeristics Bias Voltage Line Transient Response V OUT 10mV/DIV V BIAS 200mV/DIV 3071 G43 V = 1.3V 20µs/DIV 2.5V BIAS OUT OUT C = 16.9µF OUT Transient Load Response V OUT 50mV/DIV AC-COUPLED I OUT 2A/DIV ∆I = 500mA OUT C = 10µF + 4.7µF + 2.2µF ...
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... P small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically 300µA typically at V LT3071 -V differential IN OUT = 0.8V OUT = 1.8V. OUT 3071fa ...
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... Pulling EN low keeps the reference circuit active, but disables the output pass transistor and puts the LT3071 into a low power nap mode. Drive the EN pin with either a digital logic port or an open-collector NPN or an open-drain NMOS terminated with a pull-up resistor to V – 250mV. The 35k to meet the V BIAS connect EN to BIAS BIAS BIAS EN PWRGD SENSE IN LT3071 V OUT MARGA I IN MON VIOC REF/BYP ...
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... V – 0.25V BIAS + LOGIC Hi-Z STATE HIGH IF IN > – 0.9V BIAS – HIGH IF IN < AND IN > 0.75V – 0.75V HIGH IF IN < 0.25V LOGIC LOW STATE – 0.25V + LT3071 + I MON 21 – OUT 15-18 SENSE 19 PWRGD DETECT 2 REF/BYP V 3 REF 600mV MARGA 22 3070 BD – 0.25V BIAS – ...
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... The LT3071’s features permit state-of-the-art linear regula- tor performance. The LT3071 is ideal for high performance FPGAs, microprocessors, sensitive communication sup- plies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3071 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. An analog margining function allows the user to adjust system output voltage over a continuous ±10% range. The LT3071 provides an output current monitor that typically sources a current of I ...
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... The LT3071 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT3071’s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly preva- lent with higher frequency switching power supplies, the LT3071 offers superior regulation and an appreciable component cost savings ...
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... Enable Function—Turning On and Off The EN pin enables/disables the output device only. The LT3071 reference and all support functions remain active above its UVLO threshold. Pulling the EN pin BIAS low puts the LT3071 into nap mode. In nap mode, the reference circuit is active, but the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an open- collector NPN or an open-drain NMOS terminated with a pull-up resistor The pull-up resistor must be BIAS less than 35k to meet the V condition of the EN pin ...
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... The LT3071 requires a minimum output capacitance of 15µF for stability. LTC strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3071’s unity-gain bandwidth with C about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency 1/(2π√LC), which must be pushed to a frequency higher R than the regulator bandwidth. Standard MLCC capacitors are acceptable. To keep the resonant frequency greater than 1MHz, the product 1/(2π ...
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... PCB layout for the parallel output capacitor combination, but also illustrates the GND connection between the IN capacitor and the OUT capacitors to minimize the AC GND loop for fast load transients. This tight bypassing connection minimizes EMI and optimizes bypassing. Many of the applications in which the LT3071 excels, such as FPGA, ASIC processor or DSP supplies, typically require a high frequency decoupling capacitor network for the device being powered. This network generally consists of many low value ceramic capacitors in parallel. In some , will applications, this total value of capacitance may be close R to the LT3071’ ...
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... Stability and Input Capacitance The LT3071 is stable with a minimum capacitance 47µF connected to its IN pins. Use low ESR capacitors to minimize instantaneous voltage drops under large load 3071 F04 transient conditions. Large V transients may cause the regulator to enter dropout with corresponding degradation in load transient response ...
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... Under conditions of maximum the device’s power dissipation peaks at about IN OUT 3W. If ambient temperature is high enough, die junction temperature will exceed the 125°C maximum operating temperature. If this occurs, the LT3071 relies on two additional thermal safety features. At about 145°C, the PWRGD output pulls low providing an early warning of an ≤ 3.6V and BIAS impending thermal shutdown condition. At 165°C typically, ≤ 0.95V, the OUT the LT3071’ ...
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... IN threshold is exceeded, this detector circuit turns off the drive to the internal NMOS pass transistor, thereby turning off the output. The output pulls low with the load current discharging the output capacitance. This circuit’s intent is to limit and prevent back-feed current from OUT the input voltage collapses due to a fault or overload condition. Thermal Considerations The LT3071’s maximum rated junction temperature of 125°C limits its power handling capability and is domi- nated by the output current multiplied by the input/output voltage differential: I • (V – OUT IN OUT The LT3071’ ...
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... OUT sources. Tie the OUT pins of the paralleled regulators to the common load plane through a small piece of PC trace ballast or an actual surface mount sense resistor beyond the primary output capacitors of each regulator. The re- quired ballast is dependent upon the application output voltage and peak load current. The recommended ballast is that value which contributes 1% to load regulation. For example, two LT3071 regulators configured to output 1V, sharing a 10A load require 2mΩ of ballast at each output. The Kelvin SENSE pins connect to the regulator side of the ballast resistors to keep the individual control loops from conflicting with each other (see Figures 8 and 9). Keep this ballast trace area free of solder to maintain a controlled resistance. Table 4 shows a simple guideline for PCB trace resistance as a function of weight and trace width ...
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... SENSE EN LT3071 V OUT 2.2µ *X5R OR X7R CAPACITORS I NC MARGA MON VIOC REF/BYP 1k GND 1nF 0.01µF 3071 F06 Figure 6. 1.5V to 1.2V Linear Regulator LT3071 = 1V. See the Typical Performance OUT . REF/BYP remains active in nap mode, thus start-up REF V OUT 1.2V 5A 4.7µF* 10µF* V MON FULL SCALE at the RMS 3071fa ...
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... PV IN PLLLPF LTC3415EUHF NC CLKOUT PHMODE NC CLKIN MODE PGND PGND PGND PGND PGND NOTES: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3071 ( 2) ON SAME PCB POWER PLANE Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators TRACK 0.2µ 1.3V/5A SW 47µ ...
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... BIAS PWRGD SENSE OUT 2.2µF* 4.7µF* 10µF* LT3071 *X5R OR X7R CAPACITORS I MON REF/BYP 1k GND 0.01µF BIAS PWRGD SENSE OUT 2.2µF* 4.7µF* 10µF* LT3071 *X5R OR X7R CAPACITORS I MON REF/BYP 1.67k GND 0.01µF 3071 F09 V OUT 1V 4A TRACE TRACE V OUT MON ...
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... LT3071 pAckAge Description 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 TOP MARK (NOTE 6) 5.00 0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4 ...
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... REV DATE DESCRIPTION A 8/10 Swapped IN and EN pins in Figure 7 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LT3071 PAGE NUMBER 24 3071fa ...
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... LT3070 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● 1.5V to 1.2V Linear Regulator 50k PWRGD 2.2µF BIAS IN PWRGD EN SENSE LT3071 V OUT 2.2µF* 4.7µ *X5R OR X7R CAPACITORS NC I MARGA MON VIOC REF/BYP 1k GND 0.01µ ...