ncp590 ON Semiconductor, ncp590 Datasheet - Page 9

• Manufacturer Part Number: ncp590
• Description: Dual Output Ultra High Accuracy Ldo
• Manufacturer: ON Semiconductor

Output Regulator
reference and error amplifier. The output has saturation
control for regulation while the input voltage is low,
preventing over saturation. Current limit and voltage
monitors complement the regulator design to give safe
operating signals to the processor and control circuits.
only an active output driver providing current at the
regulated voltage with resistors from the regulated output
to ground (used in the feedback loop). This provides good
turn- on characteristics from the active PFET output driver,
but turn- off characteristics are determined by the output
capacitor values and impedance of the load in parallel with
the internal resistors in the feedback loop. The turn- off
time in the situation with high impedance loads will be
slow. The NCP590 has active pull- down transistors which
turn on during device turn- off creating efficient fast
turn- offs independent of loading.
Stability Considerations
provide low impedance to the input of the regulator.
determine three main characteristics of a linear regulator:
start- up delay, load transient response and loop stability.
availability,
aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
(- 25°C to -40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer's data
sheet usually provides this information.
and any ESR within the operating temperature range.
Calculating Power Dissipation in a Dual Output Linear
Regulator
regulator (Figure x) is:
P D = (V IN
+ V IN x I GND
The output is controlled by a precision trimmed
Standard linear regulator design circuitry consists of
The input capacitor C
The output or compensation capacitor C
The capacitor value and type should be based on cost,
Stability is guaranteed at values C
The maximum power dissipation for a dual output
–
V OUT1 ) x I OUT1 + (V IN
size
and
in
temperature
in Figure 3 is necessary to
OUT
(1)
–
= 0.7 mF to 4.7 mF
V OUT2 ) x I OUT2
constraints.
APPLICATION INFORMATION
outx
http://onsemi.com
helps
The
NCP590
9
where:
V
V
I
and
I
consumes at I
permissible value of R
thermal resistance section of the data sheet. Those board
areas with R
2 will keep the die temperature below 125°C. In some
cases, none of the circuit board areas will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required. The current flow and voltages are
shown in the Measurement Circuit Diagram. A chart
showing thermal resistance vs. pcb heat spreader area is
shown below.
Enable
independent pins, EN1 and EN2. A high (above the high
input threshold) on these logic level input pins causes the
outputs to turn on.
to 0.3 V above V
logic outputs from different operating voltages into these
pins. This happens when standard operating system
voltages must interface together (i.e., 5 V to 3.3 V systems).
the NCP590 operating with V
into the ENx pin can be kept to safe levels by adding a 100 k
resistor in series with the 5 V control drive voltage. This
will keep the input voltage in compliance with the
maximum ratings and will allow control of the output. Use
of this setup will affect turn- on time and will increase the
enable current higher than the input current specified in the
electrical parameter tables.
OUT
GND
IN
OUT
Once the value of P
The value of R
Enabling the two outputs is controlled by two
Normal operation allows for input voltages to these pins
For example, a 5 V control voltage is needed to control
is the maximum input voltage,
is the output current for each output in the application,
is the output voltage for each output,
is the quiescent or ground current the regulator
qJA
OUT
's less than the calculated value in equation
R
qJA
.
qJA
IN
. It is sometimes necessary to interface
can then be compared with those in the
+ (125
qJA
D(max)
can be calculated:
o
IN
C * T
is known, the maximum
= 3.6 V. The input current
A
) P
D
(eq. 1)